DS-LFSR: A BIST TPG for low switching activity

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 21, Issue 7, 2002, Pages 842-851

  Wang, Seongmoon ^a,b   Gupta, Sandeep K ^c  

^a IEEE   (United States)

^b NEC LABORATORIES AMERICA   (United States)

^c University of Southern California ^*  (United States)

Author keywords

Built in self test (BIST); Heat dissipation during test; Logic BIST; Low power testing; Low power testing, LFSR; Pseudorandom pattern testing; Switching activity during test

Indexed keywords

LINEAR FEEDBACK SHIFT REGISTERS; PSEUDORANDOM PATTERN TESTING; SWITCHING ACTIVITY; TEST PATTERN GENERATOR;

BOOLEAN FUNCTIONS; COMPUTER SIMULATION; LINEAR INTEGRATED CIRCUITS; POLYNOMIALS; SHIFT REGISTERS; SWITCHING THEORY; THEOREM PROVING;

BUILT-IN SELF TEST;

EID: 0036638353     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2002.1013896     Document Type: Article

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