High quality TPG for delay faults in look-up tables of FPGAs

Proceedings, DELTA 2004 - Second IEEE International Workshop on Electronic Design, Test and Applications

Volumn , Issue , 2004, Pages 83-88

  Girard, Patrick ^a   Héron, Olivier ^a   Pravossoudovitch, Serge ^a   Renovell, Michel ^a  

^a UNIV MONTPELLIER   (France)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION-ORIENTED TEST (AOT); DELAY FAULTS; LOOK-UP TABLES (LUT); MANUFACTURED-ORIENTED TEST (MOT);

COMPUTER SIMULATION; FLIP FLOP CIRCUITS; MULTIPLEXING; RANDOM ACCESS STORAGE; STATIC RANDOM ACCESS STORAGE; SWITCHING; TABLE LOOKUP;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 4544310842     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DELTA.2004.10052     Document Type: Conference Paper

References (18)

1. M. Abramovici, C. Stroud, C. Hamilton, S. Wijesuriya and V. Verrna, "Using Roving STARs for On-Line Testing and Diagnosis of FPGAs in Fault Tolerant Applications", Proc. IEEE Int. Test Conf., pp 973-982, 1999.
2. M. Abramovici and C. Stroud, "BIST-Based Delay-Fault Testing in FPGAs", Proc. IEEE Int. On-Line Testing Workshop, pp 131-134, 2002.
3. V. Betz, J. Rose, A. Marquardt, "Architecture Deep-Submicron FPGAs", Kluwer Academic Publishers, 1999.
4. P. Chow, S.O. Seo, J. Rose, K. Chung, G. Páez-Monzón and I. Rahardja, "The Design of an SRAM-Based Field-Programmable Gate Array, Part II: Circuit Design and Layout", Proc. IEEE Trans. on VLSI Systems, Vol. 7 No. 3, pp 321-330, 1999.
5. P. Girard, O. Héron, S. Pravossoudovitch and M. Renovell, "Defect Analysis for Delay-Fault BIST in FPGAs", Proc. IEEE Int. On-Line Testing Symp., pp 124-128, 2003.
6. P. Girard, O. Héron, S. Pravossoudovitch and M. Renovell, "Requirements for Delay Testing of Look-Up Tables in SRAM-Based FPGAs", Proc. IEEE European Test Workshop, Informal Digest, pp 313-318, 2003.
7. I.G. Harris and R. Tessier, "Diagnosis of Interconnect Faults in Cluster-Based FPGA Architectures", Proc. IEEE Int. Conf. On Computer Aided Design, pp 472-476, 2000.
8. I.G. Harris and R. Tessier, "Interconnect Testing in Cluster-Based FPGA Architectures", Proc Design Automation Conference, pp. 49-54, 2000.
9. I.G. Harris, P.R. Menon and R. Tessier, "BIST-Based Delay Path Testing in FPGA Architectures", Proc IEEE Int. Test Conf., pp 364-369, 2001.
10. W.K. Huang, F.J. Meyer, X.T. Chen and F. Lombardi, "Testing Configurable LUT-Based FPGAs", IEEE Trans. On Very Large Scale Integration Systems, Vol 6, pp 276-283, 1998.
11. A. Krasniewski, "Application-Dependent Testing of FPGA Delay Faults", in EUROMICRO99, pp. 260-267, 1999.
12. A. Krasniewski, "Exploiting Reconfigurability for Effective Detection of Delay Faults in LUT-Based FPGAs", Proc. Int. Conf. Field Programmable Logic & Applications, pp. 675-684, 2000.
13. M. Renovell, J.M. Portal, J. Figueras and Y. Zorian, "SRAM-Based FPCAs: Testing the Embedded RAM Modules", JETTA, Kluwer Academic Publisher, pp. 159-167, Vol 14, 1999.
14. M. Renovell, J.M. Portal, P. Faure, J. Figueras and Y. Zorian, "TOF: A Tool for Test Pattern Generation Optimization of an Application-Oriented Test", Proc. IEEE Asian Test Symp., pp. 323-328, 2000.
15. M. Renovell, J.M. Portal, P. Faure, J. Figueras and Y. Zorian, "IS-FPGA: A New Symmetric FPGA Architecture with Implicit Scan", Proc. IEEE Int. Test Conf., pp. 924-931, 2001.
16. C. Stroud, E. Lee and M. Abramovici, "BIST-Based Diagnostics of FPGA Logic Blocks", Proc. IEEE Int. Test Conf., pp. 539-547, 1997.
17. C. Stroud, E. Lee and M. Abramovici, "Built-in Self Test of FPGA Interconnect", Proc. IEEE Int. Test Conf., pp. 404-411, 1998.
18. Xilinx, Virtex Series Product Specification (FPGAs), San Jose, USA, v2.6, 2002.