SCOPUS 정보 검색 플랫폼

Volumn 1896, Issue , 2000, Pages 675-684

Exploiting reconfigurability for effective detection of delay faults in LUT-based FPGAs

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION THEORY; RECONFIGURABLE ARCHITECTURES; RECONFIGURABLE HARDWARE;

BLOCKING CAPABILITY; DELAY FAULTS; DETECTABILITY; INPUT-OUTPUT; RANDOM TESTING; RECONFIGURABILITY; SELF-TESTING; USER DEFINED FUNCTIONS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 84947589546 PISSN: 03029743 EISSN: 16113349 Source Type: Book Series
DOI: 10.1007/3-540-44614-1_72 Document Type: Conference Paper

Times cited : (13)

References (9)

1
- 0032099764
- Testing Configurable LUT-Based FPGA's
- Huang, W. K., Meyer, F. J., Chen, X.-T., Lombardi, F.: Testing Configurable LUT-Based FPGA's. IEEE Trans. on VLSI Systems (1998) 276-283
- (1998) IEEE Trans. On VLSI Systems , pp. 276-283
- Huang, W.K.¹ Meyer, F.J.² Chen, X.-T.³ Lombardi, F.⁴

2
- 0030652669
- Test of RAM-based FPGA: Methodology and Application to the Interconnect
- Renovell, M., Figueras, J., Zorian, Y.: Test of RAM-based FPGA: Methodology and Application to the Interconnect. Proc. 15th VLSI Test Symp. (1997) 230-237
- (1997) Proc. 15th VLSI Test Symp , pp. 230-237
- Renovell, M.¹ Figueras, J.² Zorian, Y.³

3
- 0029700620
- Built-In Self-Test of Logic Blocks in FPGAs (Finally, a Free Lunch: BIST Without Overhead!)
- Stroud, C., Konala, S., Chen, P., Abramovici, M.: Built-In Self-Test of Logic Blocks in FPGAs (Finally, a Free Lunch: BIST Without Overhead!). Proc. 14th VLSI Test Symp. (1996) 387-392
- (1996) Proc. 14th VLSI Test Symp , pp. 387-392
- Stroud, C.¹ Konala, S.² Chen, P.³ Abramovici, M.⁴

4
- 0031706224
- Rothko - A Three-Dimensional FPGA
- Leeser M. et al.: Rothko - A Three-Dimensional FPGA. IEEE Design & Test of Computers 1 (1998) 16-23
- (1998) IEEE Design & Test of Computers , vol.1 , pp. 16-23
- Leeser, M.¹

5
- 0043031898
- Design for Application-Dependent Testability of FPGAs
- Krasniewski, A.: Design for Application-Dependent Testability of FPGAs. Proc. Int'l Workshop on Logic and Architecture Synthesis (1997) 245-254
- (1997) Proc. Int'l Workshop on Logic and Architecture Synthesis , pp. 245-254
- Krasniewski, A.¹

6
- 84889013047
- Application-Dependent Testing of FPGA Delay Faults
- Krasniewski, A.: Application-Dependent Testing of FPGA Delay Faults. Proc. EUROMICRO’ 99 (1999) 260-267
- (1999) Proc. EUROMICRO’ 99 , pp. 260-267
- Krasniewski, A.¹

7
- 84947603417
- Tech. Report, Warsaw Univ. of Technology, Inst. of Telecommunications
- Krasniewski, A.: Self-Testing of FPGA Delay Faults in the System Environment. Tech. Report, Warsaw Univ. of Technology, Inst. of Telecommunications (2000)
- (2000) Self-Testing of FPGA Delay Faults in the System Environment
- Krasniewski, A.¹

8
- 84947560921
- Preprints IFAC Workshop on Programmable Devices and Systems – PDS2000
- Krasniewski, A.: Enhancing Detection of Delay Faults in FPGA-Based Circuits by Transformations of LUT Functions, Preprints IFAC Workshop on Programmable Devices and Systems – PDS2000 (2000) 127-132
- (2000) Enhancing Detection of Delay Faults in Fpga-Based Circuits by Transformations of LUT Functions , pp. 127-132
- Krasniewski, A.¹

9
- 0004001236
- Marcel Dekker, Inc
- David R.: Random Testing of Digital Circuits - Theory and Applications, Marcel Dekker, Inc. (1998)
- (1998) Random Testing of Digital Circuits - Theory and Applications
- David, R.¹

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.