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Bist test pattern generators for two-pattern testing-theory and design algorithms
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Design of efficient bist test pattern generators for delay testing
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Technology mapping for tlu fpga's based on decomposition of binary decision diagrams
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0022306482
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Pseudo-exhaustive adjacency testing: A bist approach for stuck-open faults
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On the generation of pseudo-deterministic two-patterns test sequence with lfsrs
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Testing configurable lut-based fpga's
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Universal fault diagnosis for lookup table fpgas
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Inoue, T.1
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Bist for plbs of a look-up table type fpga- A comparator based bist technique under definite fault model
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Itazaki, N.1
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Application-dependent testability of fpga-based circuits designed using functional decomposition
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Detection of delay faults in large in-system reprogrammable fpgas
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A. Krasniewski, "Detection of Delay Faults in Large In-System Reprogrammable FPGAs", in P. Puschner (ed.), Proc. 10th European Workshop on Dependable Computing, pp. 123-127, 1999.
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Rothko: A three-dimensional fpga
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Test of ram-based fpga: Methodology and application to the interconnect
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Performance-oriented technology mapping for lut-based fpga's
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Shin, H.1
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Built-in self-test of logic blocks in fpgas (finally, a free lunch: Bist without overhead!)
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Accumulator-based bist approach for stuck-open and delay fault testing
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A bist approach to delay fault testing with reduced test length
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Wurth, B.1
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22
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0004838718
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Bist generators for sequential faults
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