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Volumn 1, Issue , 1999, Pages 260-267

Application-dependent testing of FPGA delay faults

Author keywords

[No Author keywords available]

Indexed keywords

BIST TECHNIQUES; PROGRAMMABLE LOGIC; PSEUDO-EXHAUSTIVE TESTING; RANDOM TESTING; REPROGRAMMABLE; TEST PATTERN GENERATOR; TIMING CHARACTERISTICS; USER DEFINED FUNCTIONS;

EID: 84889013047     PISSN: 10896503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EURMIC.1999.794478     Document Type: Conference Paper
Times cited : (36)

References (22)
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  • 2
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    • Design of efficient bist test pattern generators for delay testing
    • Dec
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    • Chen, C.-A.1    Gupta, S.K.2
  • 3
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    • Technology mapping for tlu fpga's based on decomposition of binary decision diagrams
    • Oct
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    • Chang, S.-C.1    Marek-Sadowska, M.2    Hwang, T.T.3
  • 4
    • 0022306482 scopus 로고
    • Pseudo-exhaustive adjacency testing: A bist approach for stuck-open faults
    • G. L. Craig, C. R. Kime, "Pseudo-Exhaustive Adjacency Testing: A BIST Approach for Stuck-Open Faults", Proc. IEEE Int'l Test Conf., pp. 126-137, 1985.
    • (1985) Proc. IEEE Int'l Test Conf. , pp. 126-137
    • Craig, G.L.1    Kime, C.R.2
  • 5
    • 0030646141 scopus 로고    scopus 로고
    • On the generation of pseudo-deterministic two-patterns test sequence with lfsrs
    • C. Dufaza, Y. Zorian, "On the Generation of Pseudo-Deterministic Two-Patterns Test Sequence with LFSRs", Proc. European Design &Test Conf., 1997.
    • (1997) Proc. European Design &Test Conf.
    • Dufaza, C.1    Zorian, Y.2
  • 8
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    • Bist for plbs of a look-up table type fpga- A comparator based bist technique under definite fault model
    • N. Itazaki, Y. Matsumoto, K. Kinoshita, "BIST for PLBs of a Look-Up Table Type FPGA-A Comparator Based BIST Technique under Definite Fault Model", Proc. 3rd On-Line Testing Workshop, pp. 202-206, 1997.
    • (1997) Proc. 3rd On-Line Testing Workshop , pp. 202-206
    • Itazaki, N.1    Matsumoto, Y.2    Kinoshita, K.3
  • 10
    • 0141977486 scopus 로고    scopus 로고
    • Application-dependent testability of fpga-based circuits designed using functional decomposition
    • A. Krasniewski, M. Nowicka "Application-Dependent Testability of FPGA-Based Circuits Designed Using Functional Decomposition," Proc. IFIP Workshop on Logic and Architecture Synthesis, pp. 167-175, 1996.
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  • 13
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    • Detection of delay faults in large in-system reprogrammable fpgas
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  • 14
    • 0031706224 scopus 로고    scopus 로고
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    • Jan.-March
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  • 16
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  • 17
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  • 18
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  • 19
  • 21
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.