The design of a SRAM-based field-programmable gate array - Part II: Circuit design and layout

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 7, Issue 3, 1999, Pages 321-330

  Chow, Paul ^a,b   Seo, Soon Ong ^c   Rose, Jonathan ^a,b   Chung, Kevin ^d   Páez Monzón, Gerard ^e,f   Rahardja, Immanuel ^f,g  

^a IEEE   (Canada)

^b UNIVERSITY OF TORONTO   (Canada)

^c ADVANCED MICRO DEVICES   (United States)

^d XILINX INC   (United States)

^e NATIONAL SEMICONDUCTOR CORPORATION   (United States)

^f UNIVERSIDAD DE LOS ANDES   (Venezuela)

^g Aristo Technology Inc   (United States)

Author keywords

Field programmable gate arrays; FPGA; FPGA architecture; FPGA circuit design; SRAM programmable

Indexed keywords

ELECTRIC NETWORK SYNTHESIS; INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN; RANDOM ACCESS STORAGE;

STATIC RANDOM ACCESS MEMORY (SRAM);

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0032646901     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.784093     Document Type: Article

References (5)

1. P. Chow, S. O. Seo, J. Rose, K. Chung, G. Páez-Monzón, and I. Rahardja, "The design of an SRAM-based field-programmable gate array - Part I: Architecture," IEEE Trans. VLSI Syst., vol. 7, pp. 191-197, June 1999.
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3. C. Ebeling, G. Borriello, S. A. Hauck, D. Song, and E. A. Walkup, "TRIPTYCH: A new FPGA architecture," in FPGA's, W. Moore and W. Luk, Eds. Nashville, TN: Abingdon, 1991, ch. 3.1, pp. 75-90.
4. I. E. Sutherland and R. F. Sproull, "Logical effort: Designing for speed on the back of an envelope," in Proc. Univ. California at Santa Cruz Conf. Advanced Res. VLSI, Mar. 1991, pp. 1-16.
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