3-D placement considering vertical interconnects

Proceedings - IEEE International SOC Conference, SOCC 2003

Volumn , Issue , 2003, Pages 257-258

  Kaya, I ^a   Olbrich, M ^a   Barke, E ^a  

^a LEIBNIZ UNIVERSITY HANNOVER   (Germany)

Author keywords

CMOS technology; Delay; Electronic design automation and methodology; Integrated circuit interconnections; Microelectronics; Nonlinear equations; Routing; Vectors; Very large scale integration

Indexed keywords

ADDERS; CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; ELECTRONIC DESIGN AUTOMATION; INTEGRATED CIRCUITS; MICROELECTRONICS; NONLINEAR EQUATIONS; QUADRATIC PROGRAMMING; THREE DIMENSIONAL INTEGRATED CIRCUITS; VECTORS; VLSI CIRCUITS;

CMOS TECHNOLOGY; DELAY; ELECTRONIC DESIGN AUTOMATION AND METHODOLOGIES; INTEGRATED CIRCUIT INTERCONNECTIONS; ROUTING;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 77954469961     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOC.2003.1241509     Document Type: Conference Paper

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