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Volumn 23, Issue 12, 2002, Pages 716-718

Heating effects of clock drivers in bulk, SOI, and 3-D CMOS

Author keywords

Clock distribution; Finite element methods (FEMs); Heat dissipation; Silicon on insulator (SOI) technology; Thermal modeling; Three dimensional integrated circuits (3 DICs)

Indexed keywords

ELECTRIC CLOCKS; FINITE ELEMENT METHOD; HEAT LOSSES; INTEGRATED CIRCUIT MANUFACTURE; POWER ELECTRONICS; SILICON ON INSULATOR TECHNOLOGY; THERMAL EFFECTS; TRANSIENTS;

EID: 0037005422     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2002.805755     Document Type: Letter
Times cited : (25)

References (12)
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  • 4
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    • Goodson, K.E.1    Flik, M.I.2
  • 5
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    • Thermal analysis of vertically integrated circuits
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    • Kleiner, M.B.1    Kuhn, S.A.2    Ramm, P.3    Weber, W.4
  • 7
    • 0034452632 scopus 로고    scopus 로고
    • Full chip thermal analysis of planar (2-D) and vertically integrated (3-D) high-performance ICs
    • S. Im and K. Banerjee, "Full chip thermal analysis of planar (2-D) and vertically integrated (3-D) high-performance ICs," in IEDM Tech. Dig., 2000, pp. 727-730.
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    • Im, S.1    Banerjee, K.2
  • 8
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    • A. P. Chandrakasan, W. Bowhill, and F. Fox, Eds.; Piscataway, NJ: IEEE Press
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  • 10
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    • FIDAP; Fluent, Inc., Centerra Park Lebanon, NH. [Online]
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    • (2002)
  • 11
    • 0035158964 scopus 로고    scopus 로고
    • Multi-layers with buried structures (MLBS): An approach to three-dimensional integration
    • L. Xue, C. C. Liu, and S. Tiwari, "Multi-layers with buried structures (MLBS): An approach to three-dimensional integration," in Proc. IEEE SOI Conf., 2001, pp. 117-118.
    • Proc. IEEE SOI Conf., 2001 , pp. 117-118
    • Xue, L.1    Liu, C.C.2    Tiwari, S.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.