System design issues for 3D system-in-package (SiP)

Proceedings - Electronic Components and Technology Conference

Volumn 1, Issue , 2004, Pages 610-615

  Miettinen, Jani ^a   Mäntysalo, Matti ^a   Kaija, Kimmo ^a   Ristolainen, Eero O ^a  

^a TAMPERE UNIVERSITY OF TECHNOLOGY   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

COST EFFECTIVENESS; ELECTRONICS INDUSTRY; FREQUENCIES; INTERCONNECTION NETWORKS; MICROELECTRONICS; SYSTEMS ANALYSIS;

MASS PRODUCTION PROCESS; MULTICHIP PACKAGING; SYSTEM-ON-CHIP (SOC); THIN INTERPOSERS;

CHIP SCALE PACKAGES;

EID: 10444242508     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

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