메뉴 건너뛰기




Volumn 27, Issue 4, 2008, Pages 610-620

Variability-driven formulation for simultaneous gate sizing and postsilicon tunability allocation

Author keywords

Convex programming; Fabrication randomness; Optimality

Indexed keywords

ALGORITHMS; MICROMETERS; STATISTICAL METHODS; STOCHASTIC PROGRAMMING;

EID: 41549134131     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2008.917960     Document Type: Conference Paper
Times cited : (20)

References (24)
  • 1
    • 34547155552 scopus 로고    scopus 로고
    • Circuit optimization using statistical static timing analysis
    • A. Agrawal, K. Chopra, D. Blaauw, and V. Zolotov, "Circuit optimization using statistical static timing analysis," in Proc. DAC, 2005, pp. 338-342.
    • (2005) Proc. DAC , pp. 338-342
    • Agrawal, A.1    Chopra, K.2    Blaauw, D.3    Zolotov, V.4
  • 2
    • 34547142836 scopus 로고    scopus 로고
    • Variability-driven gate sizing for binning yield optimization
    • A. Davoodi and A. Srivastava, "Variability-driven gate sizing for binning yield optimization," in Proc. DAC, 2006, pp. 959-964.
    • (2006) Proc. DAC , pp. 959-964
    • Davoodi, A.1    Srivastava, A.2
  • 3
    • 33751394193 scopus 로고    scopus 로고
    • Statistical gate sizing for timing yield optimization
    • Nov
    • D. Sinha, N. V. Shenoy, and H. Zhou, "Statistical gate sizing for timing yield optimization," in Proc. ICCAD, Nov. 2005, pp. 1037-1041.
    • (2005) Proc. ICCAD , pp. 1037-1041
    • Sinha, D.1    Shenoy, N.V.2    Zhou, H.3
  • 6
    • 0346778721 scopus 로고    scopus 로고
    • Statistical timing analysis considering spatial correlations using a single pert-like traversal
    • H. Chang and S. Sapatnekar, "Statistical timing analysis considering spatial correlations using a single pert-like traversal," in Proc. ICCAD, 2003, pp. 621-625.
    • (2003) Proc. ICCAD , pp. 621-625
    • Chang, H.1    Sapatnekar, S.2
  • 7
    • 27944511054 scopus 로고    scopus 로고
    • Parameterized block-based statistical timing analysis with non-Gaussian parameters, nonlinear delay functions
    • H. Chang, V. Zolotov, S. Narayan, and C. Visweswariah, "Parameterized block-based statistical timing analysis with non-Gaussian parameters, nonlinear delay functions," in Proc. DAC, 2005, pp. 71-76.
    • (2005) Proc. DAC , pp. 71-76
    • Chang, H.1    Zolotov, V.2    Narayan, S.3    Visweswariah, C.4
  • 8
    • 0022231945 scopus 로고
    • TILOS: A posynomial programming approach to transistor sizing
    • J. Fishburn and A. Dunlop, "TILOS: A posynomial programming approach to transistor sizing," in Proc. ICCAD, 1985, pp. 326-328.
    • (1985) Proc. ICCAD , pp. 326-328
    • Fishburn, J.1    Dunlop, A.2
  • 9
    • 27944492787 scopus 로고    scopus 로고
    • Robust gate sizing by geometric programming
    • Jul
    • J. Singh, V. Nookala, Z. Luo, and S. Sapatnekar, "Robust gate sizing by geometric programming," in Proc. DAC, Jul. 2005, pp. 315-320.
    • (2005) Proc. DAC , pp. 315-320
    • Singh, J.1    Nookala, V.2    Luo, Z.3    Sapatnekar, S.4
  • 10
    • 16244383507 scopus 로고    scopus 로고
    • A yield improvement methodology using pre- and post-silicon statistical clock scheduling
    • J.-L. Tsai, D. Baik, C. C.-P. Chen, and K. K. Saluja, "A yield improvement methodology using pre- and post-silicon statistical clock scheduling," in Proc. ICCAD, 2004, pp. 611-618.
    • (2004) Proc. ICCAD , pp. 611-618
    • Tsai, J.-L.1    Baik, D.2    Chen, C.C.-P.3    Saluja, K.K.4
  • 11
    • 33751439543 scopus 로고    scopus 로고
    • Statistical timing analysis driven post-silicon-tunable clock-tree synthesis
    • J.-L. Tsai, L. Zhang, and C. C.-P. Chen, "Statistical timing analysis driven post-silicon-tunable clock-tree synthesis," in Proc. ICCAD, 2005, pp. 575-581.
    • (2005) Proc. ICCAD , pp. 575-581
    • Tsai, J.-L.1    Zhang, L.2    Chen, C.C.-P.3
  • 12
    • 27944441297 scopus 로고    scopus 로고
    • An efficient algorithm for statistical minimization of total power under timing yield constraints
    • Jul
    • M. Mani, A. Devgan, and M. Orshansky, "An efficient algorithm for statistical minimization of total power under timing yield constraints," in Proc. DAC, Jul. 2005, pp. 309-314.
    • (2005) Proc. DAC , pp. 309-314
    • Mani, M.1    Devgan, A.2    Orshansky, M.3
  • 13
    • 46149117523 scopus 로고    scopus 로고
    • Joint design-time and post silicon minimization of parametric yield loss using adjustable robust optimization
    • Nov
    • M. Mani, A. Singh, and M. Orshansky, "Joint design-time and post silicon minimization of parametric yield loss using adjustable robust optimization," in Proc. ICCAD, Nov. 2006, pp. 19-26.
    • (2006) Proc. ICCAD , pp. 19-26
    • Mani, M.1    Singh, A.2    Orshansky, M.3
  • 15
    • 0016084468 scopus 로고
    • Stochastic programs with fixed recourse: The equivalent deterministic program
    • Jul
    • R. J.-B. Wets, "Stochastic programs with fixed recourse: The equivalent deterministic program," SIAM Rev., vol. 16, no. 3, pp. 309-339, Jul. 1974.
    • (1974) SIAM Rev , vol.16 , Issue.3 , pp. 309-339
    • Wets, R.J.-B.1
  • 16
    • 27944502914 scopus 로고    scopus 로고
    • Leakage minimization of nano-scale circuits in the presence of systematic and random variations
    • Nov
    • S. Bhardwaj and S. B. K. Vrdhula, "Leakage minimization of nano-scale circuits in the presence of systematic and random variations," in Proc. ICCAD, Nov. 2005, pp. 541-546.
    • (2005) Proc. ICCAD , pp. 541-546
    • Bhardwaj, S.1    Vrdhula, S.B.K.2
  • 18
    • 41549118981 scopus 로고    scopus 로고
    • A statistical framework for post-silicon tuning through body-bias clustering
    • S. Kulkarni, D. Sylvester, and D. Blaauw, "A statistical framework for post-silicon tuning through body-bias clustering," in Proc. ICCAD, 2006, pp. 39-46.
    • (2006) Proc. ICCAD , pp. 39-46
    • Kulkarni, S.1    Sylvester, D.2    Blaauw, D.3
  • 19
    • 0027701389 scopus 로고
    • An exact solution to the transistor sizing problem for CMOS circuits using convex optimization
    • Nov
    • S. Sapatnekar, V. B. Rao, P. M. Vaidya, and S. M. Kang, "An exact solution to the transistor sizing problem for CMOS circuits using convex optimization," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 12, no. 11, pp. 1621-1634, Nov. 1993.
    • (1993) IEEE Trans. Comput.-Aided Design Integr. Circuits Syst , vol.12 , Issue.11 , pp. 1621-1634
    • Sapatnekar, S.1    Rao, V.B.2    Vaidya, P.M.3    Kang, S.M.4
  • 20
    • 0034317347 scopus 로고    scopus 로고
    • Clock generation and distribution for the first IA-64 microprocessor
    • Nov
    • S. Tam, S. Rusu, U. Nagarji Desai, R. Kim, J. Zhang, and I. Young, "Clock generation and distribution for the first IA-64 microprocessor, " IEEE J. Solid-State Circuits, vol. 35, no. 11, pp. 1545-1552, Nov. 2000.
    • (2000) IEEE J. Solid-State Circuits , vol.35 , Issue.11 , pp. 1545-1552
    • Tam, S.1    Rusu, S.2    Nagarji Desai, U.3    Kim, R.4    Zhang, J.5    Young, I.6
  • 21
    • 27944484876 scopus 로고    scopus 로고
    • A general framework for accurate statistical timing analysis considering correlations
    • V. Khandelwal and A. Srivastava, "A general framework for accurate statistical timing analysis considering correlations," in Proc. DAC, 2005, pp. 89-94.
    • (2005) Proc. DAC , pp. 89-94
    • Khandelwal, V.1    Srivastava, A.2
  • 22
    • 34748852011 scopus 로고    scopus 로고
    • Variability-driven formulation for simultaneous gate sizing and post-silicon tunability allocation
    • V. Khandelwal and A. Srivastava, "Variability-driven formulation for simultaneous gate sizing and post-silicon tunability allocation," in Proc. ISPD, 2007, pp. 11-18.
    • (2007) Proc. ISPD , pp. 11-18
    • Khandelwal, V.1    Srivastava, A.2
  • 23
    • 0033712799 scopus 로고    scopus 로고
    • New paradigm of predictive MOSFET and interconnect modeling for early circuit design
    • Y. Cao, T. Sato, D. Sylvester, M. Orshansky, and C. Hu, "New paradigm of predictive MOSFET and interconnect modeling for early circuit design," in Proc. CICC, 2000, pp. 201-204.
    • (2000) Proc. CICC , pp. 201-204
    • Cao, Y.1    Sato, T.2    Sylvester, D.3    Orshansky, M.4    Hu, C.5
  • 24
    • 27944484450 scopus 로고    scopus 로고
    • Correlation-aware statistical timing analysis with non Gaussian delay distributions
    • Y. Zhan, A. J. Strojwas, X. Li, L. T. Pileggi, D. Newmark, and M. Sharma, "Correlation-aware statistical timing analysis with non Gaussian delay distributions," in Proc. DAC, 2005, pp. 77-82.
    • (2005) Proc. DAC , pp. 77-82
    • Zhan, Y.1    Strojwas, A.J.2    Li, X.3    Pileggi, L.T.4    Newmark, D.5    Sharma, M.6


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.