Watermarking for intellectual property protection

Electronics Letters

Volumn 39, Issue 18, 2003, Pages 1316-1318

  Fan, Y C ^a   Tsao, H W ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

HARDWARE; INTELLECTUAL PROPERTY; ROUTERS;

SELF-TEST CIRCUITS;

DIGITAL WATERMARKING;

EID: 0141829122     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20030874     Document Type: Article

References (4)

1. CHANG, H.: 'Surviving the SOC revolution: a guide to platform-based design' (Kluwer Academic Publishers, 1999), pp. 1-30
2. KAHNG, A.B., MANTIK, S., MARKOV, I.L., POTKONJAK, M., TUCKER, P., HUIJUAN WANG and WOLFE, G.: 'Robust IP watermarking methodologies for physical design'. Design Automation Conference, 1998. Proceedings, 1998, pp. 782-787
3. NARAYAN, N., NEWBOULD, R.D., CAROTHERS, J.D., RODRIGUEZ, J.J., and HOLMAN, W.T.: 'IP protection for VLSI designs via watermarking of routes'. ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International, 2001, pp. 406-410
4. NEWBOULD, R.D., IRBY, D.L., CAROTHERS, I.D., RODRIGUEZ, J.J., and HOLMAN, W: 'Watermarking ICs for IP protection', Electron. Lett., 2002, 38, (6&14), pp. 272-274