Boundary Scan Test Scheme for IP Core Identification via Watermarking

IEICE Transactions on Information and Systems

Volumn E88-D, Issue 7, 2005, Pages 1397-1400

  Fan, Yu Cheng ^a   Tsao, Hen Wai ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

Boundary scan test scheme (BSTS); Intellectual property (IP) identification; System on a chip (SOC); VLSI design; Watermarking

Indexed keywords

DIGITAL WATERMARKING; ELECTRONICS PACKAGING; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; MICROPROCESSOR CHIPS; PHOTOGRAPHY; VLSI CIRCUITS;

BOUNDARY SCAN TEST SCHEME (BSTS); INTELLECTUAL PROPERTY (IP) IDENTIFICATION; SYSTEM ON A CHIP (SOC); VLSI DESIGN;

INTELLECTUAL PROPERTY;

EID: 26044459497     PISSN: 09168532     EISSN: 17451361     Source Type: Journal    
DOI: 10.1093/ietisy/e88-d.7.1397     Document Type: Article

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