-
1
-
-
0032204363
-
ESD protection for high frequency integrated circuits
-
G. Graph and J. Bernier, "ESD protection for high frequency integrated circuits," Solid-State Electron., vol. 38, pp. 1681-1689, 1998.
-
(1998)
Solid-state Electron.
, vol.38
, pp. 1681-1689
-
-
Graph, G.1
Bernier, J.2
-
3
-
-
0029536334
-
Bipolar SCR ESD protection for high speed submicron Bipolar/BiCMOS frequency integrated circuits
-
J. Z. Chen, A. Amerasekera, and T. Vrotos, "Bipolar SCR ESD protection for high speed submicron Bipolar/BiCMOS frequency integrated circuits," in IEDM Tech. Dig., 1995, pp. 337-340.
-
(1995)
IEDM Tech. Dig.
, pp. 337-340
-
-
Chen, J.Z.1
Amerasekera, A.2
Vrotos, T.3
-
4
-
-
0035478369
-
MOSFET triggering silicon controlled rectifiers for electrostatic discharge protection circuits
-
S. L. Jang and S. H. Li, "MOSFET triggering silicon controlled rectifiers for electrostatic discharge protection circuits," Solid-State Electron., vol. 45, pp. 1799-1803, 2001.
-
(2001)
Solid-state Electron.
, vol.45
, pp. 1799-1803
-
-
Jang, S.L.1
Li, S.H.2
-
5
-
-
0034544872
-
Electrostatic discharge characterization of epitaxial-base silicon-germanium hetro junction bipolar transistors
-
S. Voldman, N. Schmidt, R. Johnson, L. Lanzerotti, A. Joseph, C. Brennan, J. Dunn, and D. Harame, "Electrostatic discharge characterization of epitaxial-base silicon-germanium hetro junction bipolar transistors," in Proc. ESD/EOS Symp., 2000, pp. 239-250.
-
(2000)
Proc. ESD/EOS Symp.
, pp. 239-250
-
-
Voldman, S.1
Schmidt, N.2
Johnson, R.3
Lanzerotti, L.4
Joseph, A.5
Brennan, C.6
Dunn, J.7
Harame, D.8
-
8
-
-
0031274651
-
Electrical instability and filamentation in ggMOS protection structures
-
V. A. Vashchenko, Y. Martynov, and V. F. Sinkevitch, "Electrical instability and filamentation in ggMOS protection structures," Solid-State Electron., vol. 41, pp. 1761-1767, 1997.
-
(1997)
Solid-state Electron.
, vol.41
, pp. 1761-1767
-
-
Vashchenko, V.A.1
Martynov, Y.2
Sinkevitch, V.F.3
-
9
-
-
0030129156
-
Negative differential conductivity and isothermal drain breakdown of the GaAs MESFET
-
Apr.
-
V. A. Vashchenko et al., "Negative differential conductivity and isothermal drain breakdown of the GaAs MESFET," IEEE Trans. Electron Devices, vol. 43, pp. 513-518, Apr. 1996.
-
(1996)
IEEE Trans. Electron Devices
, vol.43
, pp. 513-518
-
-
Vashchenko, V.A.1
-
10
-
-
0034538958
-
Breakdown and latent damage of ultra-thin gate oxides under ESD stress conditions
-
J. Wu, P. Juliano, and E. Rosenbaum, "Breakdown and latent damage of ultra-thin gate oxides under ESD stress conditions," in Proc. ESD/EOS Symp., 2000, pp. 287-295.
-
(2000)
Proc. ESD/EOS Symp.
, pp. 287-295
-
-
Wu, J.1
Juliano, P.2
Rosenbaum, E.3
-
11
-
-
0037509662
-
The impact of substrate resistivity on ESD protection devices
-
T. Smedes, A. Heringa, J. van Zwol, and P. C de Jong, "The impact of substrate resistivity on ESD protection devices," in Proc. ESD/EOS Symp., 2002, pp. 354-361.
-
(2002)
Proc. ESD/EOS Symp.
, pp. 354-361
-
-
Smedes, T.1
Heringa, A.2
Van Zwol, J.3
De Jong, P.C.4
-
12
-
-
0031357311
-
An attempt to explain thermally induced soft failures during low level ESD stresses: Study of the differences between soft and hard NMOS failures
-
P. Salome, C. Leroux, D. Mariolle, D. Lafond, J. P. Chante, J. P. Crevel, and G. Reimbold, "An attempt to explain thermally induced soft failures during low level ESD stresses: study of the differences between soft and hard NMOS failures," in Proc. ESD/EOS Symp., 1997, pp. 337-345.
-
(1997)
Proc. ESD/EOS Symp.
, pp. 337-345
-
-
Salome, P.1
Leroux, C.2
Mariolle, D.3
Lafond, D.4
Chante, J.P.5
Crevel, J.P.6
Reimbold, G.7
-
13
-
-
0036437982
-
Comparison of ESD protection capability of lateral BJT, SCR and bi-directional SCR for high-voltage BiCMOS circuits
-
V. A. Vashchenko, A. Concannon, M. ter Beek, and P. Hopper, "Comparison of ESD protection capability of lateral BJT, SCR and bi-directional SCR for high-voltage BiCMOS circuits," in Proc. Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), 2002, pp. 181-184.
-
(2002)
Proc. Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)
, pp. 181-184
-
-
Vashchenko, V.A.1
Concannon, A.2
Ter Beek, M.3
Hopper, P.4
-
14
-
-
84948982831
-
GGSCR's: GGNMOS triggered silicon controlled rectifiers for ESD protection in deep sub-micron
-
C. C. Russ, P. J. Mergens, K. G. Verhaege, J. Armer, P. C. Jozwiak, G. Kolluri, and L. R. Avery, "GGSCR's: GGNMOS triggered silicon controlled rectifiers for ESD protection in deep sub-micron," in Proc. ESD/EOS Symp., 2001, pp. 22-31.
-
(2001)
Proc. ESD/EOS Symp.
, pp. 22-31
-
-
Russ, C.C.1
Mergens, P.J.2
Verhaege, K.G.3
Armer, J.4
Jozwiak, P.C.5
Kolluri, G.6
Avery, L.R.7
-
15
-
-
0034159376
-
Cascoded LVTSCR with tunable holding voltage for ESD protection in bulk CMOS technology without latchup dange
-
M. Ker and H. Chang, "Cascoded LVTSCR with tunable holding voltage for ESD protection in bulk CMOS technology without latchup dange," Solid-State Electron., vol. 44, pp. 425-445, 2000.
-
(2000)
Solid-state Electron.
, vol.44
, pp. 425-445
-
-
Ker, M.1
Chang, H.2
-
16
-
-
84948778506
-
Technology CAD evaluation of BiCMOS protection structures operation including spatial thermal runaway
-
V. A. Vashchenko, A. Concannon, M. ter Beek, and P. Hopper, "Technology CAD evaluation of BiCMOS protection structures operation including spatial thermal runaway," in Proc. ESD/EOS Symp., 2002, pp. 101-110.
-
(2002)
Proc. ESD/EOS Symp.
, pp. 101-110
-
-
Vashchenko, V.A.1
Concannon, A.2
Ter Beek, M.3
Hopper, P.4
-
17
-
-
0037509660
-
High holding current SCR's (HHI-SCR) for ESD protection and latch-up immune IC operation
-
M. Mergens, C. Russ, K. Verhaege, J. Armer, P. Jozwiak, and R. Mohn, "High holding current SCR's (HHI-SCR) for ESD protection and latch-up immune IC operation," in Proc. ESD/EOS Symp., 2002, pp. 11-17.
-
(2002)
Proc. ESD/EOS Symp.
, pp. 11-17
-
-
Mergens, M.1
Russ, C.2
Verhaege, K.3
Armer, J.4
Jozwiak, P.5
Mohn, R.6
-
18
-
-
0037972775
-
Increasing the ESD protection capability of over-voltage NMOS structures by comb-ballasting region design
-
V. A. Vashchenko, A. Concannon, M. ter Beek, and P. Hopper, "Increasing the ESD protection capability of over-voltage NMOS structures by comb-ballasting region design," in Proc. Int. Reliability Physics Symp., 2003, pp. 261-268.
-
(2003)
Proc. Int. Reliability Physics Symp.
, pp. 261-268
-
-
Vashchenko, V.A.1
Concannon, A.2
Ter Beek, M.3
Hopper, P.4
-
19
-
-
0034428062
-
Perspectives on technology and technology-driven CAD
-
Dec.
-
R. W. Dutton and A. J. Strojwas, "Perspectives on technology and technology-driven CAD," IEEE Trans. Computer-Aided Design, vol. 19, pp. 1544-1560, Dec. 2000.
-
(2000)
IEEE Trans. Computer-aided Design
, vol.19
, pp. 1544-1560
-
-
Dutton, R.W.1
Strojwas, A.J.2
-
20
-
-
0034542055
-
Advanced 2D/3D ESD device simulation - A powerful tool already used in a pre-Si Phase
-
K. Esmark, W. Stadler, M. Wendel, H. Gobner, X. Guggenmos, and W. Fichtner, "Advanced 2D/3D ESD device simulation - A powerful tool already used in a pre-Si Phase," in Proc. ESD/EOS Symp., 2000, pp. 420-429.
-
(2000)
Proc. ESD/EOS Symp.
, pp. 420-429
-
-
Esmark, K.1
Stadler, W.2
Wendel, M.3
Gobner, H.4
Guggenmos, X.5
Fichtner, W.6
|