-
1
-
-
33644661238
-
Content-addressable memory (CAM) circuits and architectures: A tutorial and survey
-
Mar
-
K. Pagiamtzis and A. Sheikholeslami, "Content-addressable memory (CAM) circuits and architectures: A tutorial and survey." IEEE J. Solid-State Circuits, vol. 41, no. 3, pp. 712-727, Mar. 2006.
-
(2006)
IEEE J. Solid-State Circuits
, vol.41
, Issue.3
, pp. 712-727
-
-
Pagiamtzis, K.1
Sheikholeslami, A.2
-
2
-
-
0035369412
-
A design for high-speed-low power CMOS fully parallel content-addressable memory macros
-
Jun
-
H. Miyatake, M. Tanaka, and Y. Mori, "A design for high-speed-low power CMOS fully parallel content-addressable memory macros." IEEE J. Solid-State Circuits, vol. 36. no. 6, pp. 956-968, Jun. 2001.
-
(2001)
IEEE J. Solid-State Circuits
, vol.36
, Issue.6
, pp. 956-968
-
-
Miyatake, H.1
Tanaka, M.2
Mori, Y.3
-
3
-
-
0037245512
-
A ternary content-addressable memory (TCAM) based on 4T static storage and including a current-race sensing scheme
-
Jan
-
I. Arsovski, T. Chandler, and A. Sheikholeslami, "A ternary content-addressable memory (TCAM) based on 4T static storage and including a current-race sensing scheme," IEEE J. Solid-State Circuits, vol. 38, no. 1, pp. 155-158, Jan. 2003.
-
(2003)
IEEE J. Solid-State Circuits
, vol.38
, Issue.1
, pp. 155-158
-
-
Arsovski, I.1
Chandler, T.2
Sheikholeslami, A.3
-
4
-
-
0242551718
-
A mismatch-dependent power allocation technique for match-line sensing in content-addressable memories
-
Nov
-
I. Arsovski and A. Sheikholeslami, "A mismatch-dependent power allocation technique for match-line sensing in content-addressable memories." IEEE J. Solid-State Circuits, vol. 38. no. 11, pp. 1958-1966. Nov. 2003.
-
(2003)
IEEE J. Solid-State Circuits
, vol.38
, Issue.11
, pp. 1958-1966
-
-
Arsovski, I.1
Sheikholeslami, A.2
-
5
-
-
0141509028
-
Design and analysis of low power cache using two-level filter scheme
-
Aug
-
Y. J. Chang, S. J. Ruan, and F. Lai, "Design and analysis of low power cache using two-level filter scheme," IEEE Trans. Veiy Large Scale Integr. (VLSI) Syst., vol. 11, no. 4, pp. 568-580. Aug. 2003.
-
(2003)
IEEE Trans. Veiy Large Scale Integr. (VLSI) Syst
, vol.11
, Issue.4
, pp. 568-580
-
-
Chang, Y.J.1
Ruan, S.J.2
Lai, F.3
-
7
-
-
16244390216
-
Location cache: A low-powre L2 cache system
-
Apr
-
R. Min, W. B. Jone, and Y. Hu, "Location cache: A low-powre L2 cache system," in Proc. Int. Symp. Low Power Electron. Des., Apr. 2004, pp. 120-125.
-
(2004)
Proc. Int. Symp. Low Power Electron. Des
, pp. 120-125
-
-
Min, R.1
Jone, W.B.2
Hu, Y.3
-
9
-
-
0037389024
-
A low-power precomputation-based fully parallel content-addressable memory
-
Apr
-
C. S. Lin. J. C. Chang, and B. D. Liu, "A low-power precomputation-based fully parallel content-addressable memory," IEEE J. Solid-State Circuits, vol. 38, no. 4, pp. 622-654, Apr. 2003.
-
(2003)
IEEE J. Solid-State Circuits
, vol.38
, Issue.4
, pp. 622-654
-
-
Lin, C.S.1
Chang, J.C.2
Liu, B.D.3
-
10
-
-
4344578575
-
Static divided word matching line for low-power content addressable memory design
-
May
-
K. H. Cheng, C. H. Wei, and S. Y. Jiang, "Static divided word matching line for low-power content addressable memory design." in Proc. IEEE Int. Symp. Circuits Syst., May 2004, vol. 2, pp. 23-26.
-
(2004)
Proc. IEEE Int. Symp. Circuits Syst
, vol.2
, pp. 23-26
-
-
Cheng, K.H.1
Wei, C.H.2
Jiang, S.Y.3
-
11
-
-
18744362776
-
A large-scale and low-power CAM architecture featuring a one-hot-spot block code for IP-address lookup in a network router
-
Apr
-
S. Hanzawa, T. Sakata, K. Kajigaya, R. Takemura, and T. Kawahara, "A large-scale and low-power CAM architecture featuring a one-hot-spot block code for IP-address lookup in a network router," IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 853-861, Apr. 2005.
-
(2005)
IEEE J. Solid-State Circuits
, vol.40
, Issue.4
, pp. 853-861
-
-
Hanzawa, S.1
Sakata, T.2
Kajigaya, K.3
Takemura, R.4
Kawahara, T.5
-
12
-
-
3843143905
-
A high-speed and low-voltage associative co-processor with exact Hamming/Manhattan-distance estimation using word-parallel and hierarchical search architecture
-
Aug
-
Y. Oike, M. Ikeda, and K. Asada, "A high-speed and low-voltage associative co-processor with exact Hamming/Manhattan-distance estimation using word-parallel and hierarchical search architecture," IEEE J. Solid-State Circuits, vol. 39, no. 8, pp. 1383-1387, Aug. 2004.
-
(2004)
IEEE J. Solid-State Circuits
, vol.39
, Issue.8
, pp. 1383-1387
-
-
Oike, Y.1
Ikeda, M.2
Asada, K.3
-
13
-
-
4444255844
-
A low-power content-addressable memory (CAM) using pipelined hierarchical search scheme
-
Sep
-
K. Pagiamtzis and A. Sheikholeslami, "A low-power content-addressable memory (CAM) using pipelined hierarchical search scheme." IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1512-1519, Sep. 2004.
-
(2004)
IEEE J. Solid-State Circuits
, vol.39
, Issue.9
, pp. 1512-1519
-
-
Pagiamtzis, K.1
Sheikholeslami, A.2
-
14
-
-
34248555123
-
A built-in self-test method for write-only content addressable memories
-
D. K. Bhavsar, "A built-in self-test method for write-only content addressable memories," in Proc. 23rd IEEE VLSI Test Symp.. 2005, pp. 9-14.
-
(2005)
Proc. 23rd IEEE VLSI Test Symp
, pp. 9-14
-
-
Bhavsar, D.K.1
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