A built-in self-test method for write-only content addressable memories

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2005, Pages 9-14

  Bhavsar, Dilip K ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LINEAR FEEDBACK SHIFT REGISTERS; PSEUDO RANDOM PATTERN; SELF TEST; TEST ALGORITHMS;

ASSOCIATIVE STORAGE; CAMS; INTEGRATED CIRCUIT TESTING; SHIFT REGISTERS;

BUILT-IN SELF TEST;

EID: 34248555123     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2005.7     Document Type: Conference Paper

References (5)

1. G. L. Giles, "A Methodology for Testing Content Addressable Memories," Int'l Test Conf., pp. 471-474, November 1985.
2. Y. Zorian, "An Efficient Built-in Self-Test Scheme for Content Addressable Memories," IEEE BIST Workshop, Kiawah Island, SC, March 1992.
3. J.-F. Li, R.-S. Tzeng and C.-W. Wu, "Testing and Diagnosing Embedded Content Addressable Memories," VLSI Test Symp., pp. 389-394, April 2002.
4. K.-J. Lin and C.-W. Wu, "Testing Content-Addressable Memories Using Functional Fault Models and March-Like Algorithms," IEEE Trans. Computer Aided Design of Integrated Circuits and Systems, vol. 19, no. 5, pp. 577-588, May 2000.
5. A. K. Jain, et. al., "A 1. 2GHz Alpha Microprocessor with 44. 8 GB/sec of Chip pin Bandwidth," Int'l Solid State Circuits Conf., pp. 240-241, February 2001.