Location cache: A low-power L2 cache system

Proceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04

Volumn , Issue , 2004, Pages 120-125

  Min, Rui ^a   Jone, Wen Ben ^a   Hu, Yiming ^a  

^a 705 Engineering Research Center   (United States)

Author keywords

Data location; L1 L2 caches; Set associative caches; TLB

Indexed keywords

DATA LOCATION; L1/L2 CACHES; SET-ASSOCIATIVE CACHES; TLB ADDRESS TRANSLATION;

BENCHMARKING; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; ENERGY UTILIZATION; PROGRAM PROCESSORS; RANDOM ACCESS STORAGE;

CACHE MEMORY;

EID: 16244390216     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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