A high-speed and low-voltage associative co-processor with exact Hamming/Manhattan-distance estimation using word-parallel and hierarchical search architecture

IEEE Journal of Solid-State Circuits

Volumn 39, Issue 8, 2004, Pages 1383-1387

  Oike, Yusuke ^a   Ikeda, Makoto ^a   Asada, Kunihiro ^a  

^a UNIVERSITY OF TOKYO   (Japan)

Author keywords

Associative co processor; Content addressable memory (CAM); Hamming distance; Hierarchical search; Logic in memory architecture; Manhattan distance; Word parallel

Indexed keywords

ASSOCIATIVE STORAGE; CMOS INTEGRATED CIRCUITS; DATA PROCESSING; DATA REDUCTION; DATA STORAGE EQUIPMENT; DIGITAL SIGNAL PROCESSING; ELECTRIC CLOCKS; ELECTRIC POTENTIAL; ENCODING (SYMBOLS); LOGIC CIRCUITS; LOGIC DEVICES; SIGNAL PROCESSING;

ASSOCIATIVE CO-PROCESSORS; CONTENT ADDRESSABLE MEMORY (CAM); HAMMING DISTANCE; HIERARCHICAL SEARCH; LOGIC-IN-MEMORY ARCHITECTURE; MANHATTAN DISTANCE; WORD PARALLEL;

ELECTRIC CURRENTS;

EID: 3843143905     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2004.831805     Document Type: Article

References (5)

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