Design and Analysis of Low-Power Cache Using Two-Level Filter Scheme

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 11, Issue 4, 2003, Pages 568-580

  Chang, Yen Jen ^a   Ruan, Shanq Jang ^a,b   Lai, Feipei ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

^b SYNOPSYS INC   (Taiwan)

Author keywords

Block buffer; Filter scheme; Low power cache; Power consumption; Unnecessary cache activity

Indexed keywords

BUFFER STORAGE; ENERGY EFFICIENCY; ENERGY UTILIZATION; ESTIMATION;

LOW-POWER CACHE;

VLSI CIRCUITS;

EID: 0141509028     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2003.812292     Document Type: Article

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