Using cache to reduce power in Content-Addressable Memories (CAMs)

Proceedings of the Custom Integrated Circuits Conference

Volumn 2005, Issue , 2005, Pages 369-372

  Pagiamtzis, Kostas ^a   Sheikholeslami, Ali ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; CMOS INTEGRATED CIRCUITS; LOGIC DESIGN; MICROPROCESSOR CHIPS; SILICON;

CACHE HIT RATE; SILICON AREA; TESTCHIP;

ASSOCIATIVE STORAGE;

EID: 33847143257     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2005.1568682     Document Type: Conference Paper

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