Dynamic filter cache for low power instruction memory hierarchy

Proceedings of the EUROMICRO Systems on Digital System Design, DSD 2004

Volumn , Issue , 2004, Pages 607-610

  Vivekanandarajah, Kugan ^a   Srikanthan, Thambipillai ^a   Bhattacharyya, Saurav ^a  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMIC POWER REDUCTION; FILTER CACHE (FC); INSTRUCTION SET ARCHITECTURE (ISA); PERFORMANCE DEGRADATION;

ALGORITHMS; COMPUTER SIMULATION; CONTROL EQUIPMENT; ENERGY EFFICIENCY; ENERGY UTILIZATION; OPTIMIZATION; ROBUSTNESS (CONTROL SYSTEMS); VLSI CIRCUITS;

BUFFER STORAGE;

EID: 13944261189     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2004.1333333     Document Type: Conference Paper

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