A robust all-wet-etching process for mesa formation of InGaAs-InP HBT featuring high uniformity and high reproducibility

IEEE Transactions on Electron Devices

Volumn 51, Issue 8, 2004, Pages 1234-1240

  Yanagisawa, Masaki ^a   Kotani, Kenji ^b   Kawasaki, Takeshi ^b   Yamabi, Ryuji ^b   Yaegassi, Seiji ^b   Yano, Hiroshi ^b  

^a SUMITOMO ELECTRIC INDUSTRIES LTD   (Japan)

^b Sumitomo Electric Device Innovations USA   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT OSCILLATIONS; ELECTRIC CURRENTS; ETCHING; INTEGRATED CIRCUITS; OPTIMIZATION; PROCESS CONTROL; SEMICONDUCTING INDIUM GALLIUM ARSENIDE; SEMICONDUCTING INDIUM PHOSPHIDE; SEMICONDUCTOR DEVICE STRUCTURES;

CURRENT GAIN; HIGH SPEED ELECTRONICS; OSCILLATION FREQUENCY; WET ETCHING;

HETEROJUNCTION BIPOLAR TRANSISTORS;

EID: 3943063655     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2004.832709     Document Type: Article

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