Over a 40 Gbit/s 16:1 multiplexer IC using InP/InGaAs HBT technology

Electronics Letters

Volumn 39, Issue 12, 2003, Pages 911-913

  Ishii, K ^a   Nakajima, H ^a   Nosaka, H ^a   Ida, M ^a   Kurishima, K ^a   Yamahata, S ^a   Enoki, T ^a   Shibata, T ^a  

^a NTT CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CURRENT DENSITY; HETEROJUNCTION BIPOLAR TRANSISTORS; OPTIMIZATION; SEMICONDUCTING INDIUM GALLIUM ARSENIDE; SEMICONDUCTING INDIUM PHOSPHIDE;

COLLECTOR CURRENT DENSITY; LIM; MEDIUM SCALE INTEGRATION CIRCUITS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0038545644     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20030596     Document Type: Article

References (7)

1. Mokhtari, M., Fields, C., and Rajavel, R.D.; '100 + GHz static divide-by-2 circuit in InP-DHBT technology'. GaAs IC Symp. Tech. Dig., Scottsdale, AZ, USA, 2002, pp. 291-293
2. Ishii, K., Nosaka, H., Ida, M., Kurishima, K., Enoki, T., Shibata, T., and Sano, E.: 'High-input-sensitivity, low-power 43 Gbit/s decision circuit using InP/InGaAs DHBTs', Electron. Lett., 2002, 38 557-558
3. Mattia, J.P., Pullela, R., Georgieu, G., Baeyens, Y., Tsai, H.S., Chen, Y.K., Dorschky, C., Winkler Von Mohrenfels, T., Reinhold, T., Groepper, C., Sokolich, M., Nguyen, L., and Stanchina, W.: 'High-speed multiplexer: a 50 Gb/s 4:1 MUX in InP HBT technology'. GaAs IC Symp. Tech. Dig., Monterey, CA, USA, 1999, pp. 189-192
4. Mattia, J.P., Pullela, R., Baeyens, Y., Chan, Y.-K., Tsai H.-S., Georgiou, G., Winkler Von Mohrenfels, T., Reinhold, M., Groepper, C., Dorschky, C., and Schulien, C.: 'A 1:4 demultiplexer for 40 Gb/s fiber-optic applications'. IEEE ISSCC Dig. Tech. Papers, San Francisco, CA, USA, 2000, pp. 64-65
5. Hendarman, A., Sovero, E.A., Xu, X., and Witt, K.: 'STS-768 multiplexer with full rate output data retimer in InP HBT'. GaAs IC Symp. Tech. Dig., Scottsdale, AZ, USA, 2002, pp. 211-214.
6. Ida, M., Kurishima, K., Nakajima, H., Watanabe, N., and Yamahata, S.; 'Undoped-emitter InP/InGaAs HBTs for high-speed and low power applications', Tech. Dig. Int. Electron Device Mtg (IEDM), 2000, pp. 854-856
7. Ishii, K., Nosaka, H., Nakajima, H., Kurishima, K., Ida, M., Watanabe, N. Yamane, Y.; Sano, E., and Enoki, T. 'Low-power 1:16 DEMUX and one-chip CDR with 1:4 DEMUX using InP-InGaAs heterojunction bipolar transistors', IEEE J. Solid-State Circuits, 2002, 37, pp. 1146-1151