A low-jitter mutual-correlated pulsewidth control loop circuit

IEEE Journal of Solid-State Circuits

Volumn 39, Issue 8, 2004, Pages 1366-1369

  Lin, Wei Ming ^a   Huang, Hong Yi ^a  

^a FU JEN CATHOLIC UNIVERSITY   (Taiwan)

Author keywords

Clocks; CMOS integrated circuits; Duty cycle; Jitter; Phase locked loops; Pulsewidth control loop circuit

Indexed keywords

BUFFER CIRCUITS; CMOS INTEGRATED CIRCUITS; DIRECT DIGITAL CONTROL SYSTEMS; ELECTRIC LOSSES; ELECTRIC POTENTIAL; MICROPROCESSOR CHIPS; OSCILLISTORS; PHASE LOCKED LOOPS; SIGNAL ENCODING; TIMING JITTER; TRANSCONDUCTANCE; VOLTAGE CONTROL;

CHARGE PUMP CIRCUITS; DUTY CYCLE; PULSEWIDTH CONTROL LOOP CIRCUIT; WIDE-RANGE FREQUENCIES;

ELECTRIC CLOCKS;

EID: 3843098221     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2004.831499     Document Type: Article

References (6)

1. J.-S. Wang, C.-F. Hu, and Y.-M. Wang, "An All-Digital Pulse-Width Locked Loop," M.S. Thesis, Department of Electrical Engineering National Chung Cheng University, Taiwan, 2002.
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