All-digital delay-locked loop/pulsewidth-control loop with adjustable duty cycles

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 6, 2006, Pages 1262-1274

  Wang, You Jen ^b   Kao, Shao Ku ^b   Liu, Shen Iuan ^a,b  

^a IEEE   (Taiwan)

^b NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

Delay locked loop (DLL); Duty cycle and time to digital conversion; Pulsewidth control loop

Indexed keywords

DELAY-LOCKED LOOP (DLL); DUTY CYCLE AND TIME-TO-DIGITAL CONVERSION; INPUT CLOCK; PULSEWIDTH-CONTROL LOOP (PWCL);

CIRCUIT THEORY; CMOS INTEGRATED CIRCUITS; ELECTRIC CLOCKS; FREQUENCY MODULATION; PHASE LOCKED LOOPS;

DIGITAL DEVICES;

EID: 33746587076     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.874326     Document Type: Article

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