Comparative analysis of double-edge versus single-edge triggered clocked storage elements

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 5, Issue , 2002, Pages

  Nedovic, Nikola ^a   Aleksic, Marko ^a   Oklobdzija, Vojin G ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CLOCKS; FLIP FLOP CIRCUITS; PULSE GENERATORS; TIMING CIRCUITS;

DOUBLE EDGE TRIGGERED CLOCKED STORAGE ELEMENTS; SINGLE EDGE TRIGGERED CLOCKED STORAGE ELEMENTS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0036293046     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. A 2.2W, 80MHz superscalar RISC microprocessor
2. Low power, testable dual edge triggered flip-flops
3. Clocked CMOS calculator circuitry
4. Reduced implementation of D-type DET flip-flops
5. Low power double edge-triggered flip-flop using one latch
6. High-speed CMOS circuit technique
7. Double-edge-triggered D-flip-flops for high-speed CMOS circuits
8. Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems
9. Timing characterization of dual-edge triggered flip-flops
10. High-performance system design: Circuits and logic