Low-voltage pulsewidth control loops for SOC applications

IEEE Journal of Solid-State Circuits

Volumn 37, Issue 10, 2002, Pages 1348-1351

  Yang, Po Hui ^a,b   Wang, Jinn Shyan ^a,b  

^a IEEE   (Taiwan)

^b NATIONAL CHUNG CHENG UNIVERSITY   (Taiwan)

Author keywords

DLL; Low voltage; PLL; Pulsewidth control loop; SOC

Indexed keywords

CLOCK FREQUENCY; DELAY LOCKED LOOP; LOW VOLTAGE CONTROL; PULSEWIDTH CONTROL; SYSTEM ON CHIP;

CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; DESIGN FOR TESTABILITY; ELECTRIC FREQUENCY CONTROL; MICROELECTRONIC PROCESSING; MICROPROCESSOR CHIPS; MULTIPLYING CIRCUITS; PULSE GENERATORS; PULSE SHAPING CIRCUITS; VOLTAGE CONTROL;

PHASE LOCKED LOOPS;

EID: 0036773083     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2002.803050     Document Type: Article

References (5)

1. F. Mu and C. Svensson, "Pulsewidth control loop in high-speed CMOS clock buffers," IEEE J. Solid-State Circuits, vol. 35, pp. 134-141, Feb. 2000.
2. P. Larsson, "A 2-1600-MHz CMOS clock recovery PLL with low-Vdd capability," IEEE J. Solid-State Circuits, vol. 34, pp. 1951-1960, Dec. 1999.
3. Y. Moon, J. Choi, K. Lee, D. K. Jeong, and M. K. Kim, "An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance," IEEE J. Solid-State Circuits, vol. 35, pp. 377-384, Mar. 2000.
4. TSMC 0.35-μm ASIC process technical digest, Taiwan Semiconductor Manufacturing Corporation, Hsin-chu, Taiwan, R.O.C, 1996.
5. J.-S. Wang, P.-H. Yang, and D. Sheng, "Design of a 3-V 300-MHz low-power 8-b × 8-b pipelined multiplier using pulse-triggered TSPC flip-flop," IEEE J. Solid-State Circuits, vol. 35, pp. 583-592, Apr. 2000.