Delay locked loop with linear delay element

TELSIKS 2005 - 7th International Conference on Telecommunications in Moderm Satellite, Cable and Broadcasting Services, Proceedings of Papers

Volumn 2, Issue , 2005, Pages 397-400

  Jovanović, Goran ^a   Stojĉev, Mile ^a   Krstić, Dragiŝa ^a  

^a Faculty of Electronic Engineering

Author keywords

CMOS circuits design; Delay; DLL

Indexed keywords

CLOCKS; CMOS INTEGRATED CIRCUITS; COMPUTER HARDWARE; COMPUTER SIMULATION; JITTER; LINEAR SYSTEMS; PARAMETER ESTIMATION;

CLOCK DISTRIBUTION NETWORK; DLL; LINEAR DELAY ELEMENT; SYNCHRONOUS DIGITAL SYSTEMS;

PHASE LOCKED LOOPS;

EID: 33846202100     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. Y.Moon, et al., "An All-Analog Multiphase Delay-Locked Loop Using a Replica Delay Line for Wide-Range Operation and Low-Jitter Performance", IEEE JSSC, vol.35, No. 3, pp. 377-384, March 2000.
2. A. Hatakeyama, et al., "A 256-Mb SDRAM Using a Register-Controlled Digital DLL", IEEE JSSC, vol. 32, No. 11, 1997.
3. S. Sidiropoulos and M. Horowitz, "A Semidigital Dual Delay-Locked Loop", IEEE JSSC, vol. 32, No. 11, pp. 1683-1692, November 1997.
4. E. Song, et al., "A Reset-Free Anti-Harmonic Delay-Locked Loop Using a Cycle Period Detector", IEEE JSSC, vol. 39, No. 11, pp. 2055-2061, November 2004.
5. G. Jovanović, M. Stojćev, "Voltage Controlled Delay Line for Digital Signal", Facta Universitatis, Series: Electronics and Energetic, vol. 16. No. 2, pp. 215-232, August 2003.
6. K. Bult, H.Wallinga, "A Class of Analog CMOS Circuits Based on the Square-Law Characteristic of an MOS Transistor in Saturation", IEEE JSSC, vol. 22, No.3, pp. 357-365, June 1987.