Record-low on-Resistance for 035 um based integrated XtreMOSTM Transistors

Proceedings of the International Symposium on Power Semiconductor Devices and ICs

Volumn , Issue , 2007, Pages 57-60

  Moens, P ^a   Bauwens, F ^a   Desoete, B ^a   Baele, J ^a   Vershinin, K ^b   Ziad, H ^a   Shankara Narayanan, E M ^b   Tack, M ^a  

^a ON SEMICONDUCTOR   (United States)

^b DE MONTFORT UNIVERSITY   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

SEMICONDUCTOR JUNCTIONS; TECHNOLOGY TRANSFER; TRANSISTORS;

INTEGRATED SMART POWER TRANSISTORS; TRENCH TECHNOLOGY;

MOS DEVICES;

EID: 39049104339     PISSN: 10636854     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISPSD.2007.4294931     Document Type: Conference Paper

References (19)

1. J. Appels and H. Vaes, "HV thin layer devices (resurf devices)", IEDM Techn. Dig., 1979, pp. 238-241.
2. T. Fujihira, "Theory of semiconductor superjunction devices", Jpn. J. Appl. Phys, 36, pp. 6254-6262 (1997).
3. R.P. Zingg, "On the specific on-resistance of high-voltage and power devices", IEEE Trans. On Elec. Devices, 51, pp. 492-499 (2004).
4. Y.C. Liang, K.P. Gan and G.S. Samudra, "Oxide bypassed VDMOS : an alternative to super-junction high voltage MOS power devices", IEEE Electron Dev. Letters, 22, pp. 407-409 (2001).
5. M. Gadja et al. "Industrialization of resurf stepped oxide technology for power transistors", Int. Symp. on Power Sem Dev, 2006, pp. 109-112.
6. P. Moens et al., "XtreMOS : The First Integrated Power Transistor Breaking the Silicon Limit", IEDM Techn. Dig., 2006, pp. 919-922.
7. A. De Smet, P. Moens and F. Bauwens, "Investigation of novel very deep trench isolation structures", Int. Symp. on Power Sem., 2006, pp. 73-78.
8. B. Desoete et al., "A Fast and Flexible Thermal Simulation Tool Validated on Smart Power Devices", Int. Symp. on Power Sem Dev, 2005. pp. 111-114.
9. G. Van den bosch et al., "Characterisation of Dynamic SOA of Power MOSFETs Limited by Electrothermal Breakdown", Proc. ESSDERC, 2005, pp. 465-468.
10. M. Kodoma, E. Hayashi, Y. Nishibe and T. Uessugi, "Temperature characteristics of a new 100V rated power MOSFET, VLMOS"., Int. Symp. on Power Sent Dev, 2004, pp. 463-466.
11. V. Khemka et al., "Novel fresurf LDMOSFET devices with improved BVDss-RDSon", IEEE Electron Device Letters, 25, pp. 804-806 (2004).
12. M. Gadja el al. "Industrialization of resurf stepped oxide technology for power transistors",. Int. Symp. on Power Sem Dev, 2006, pp. 109-112.
13. R. Van Daelen and C. Rochefort, "Vertical muhi-resurf MOSFETS exhibiting record-low specific resistance", IEDM Techn. Dig., 2003, pp. 737-740.
14. H. Yamaguchi et al., "Breakthrough of on-resistance Si Limit by Super 3D MOSFET under 100V Breakdown Voltage", Int. Symp. on Power Sem Dev, 2006, pp. 61-64.
15. H. Takaya et al., "Floating Island and Thick Bottom Oxide Trench Gate MOSFET (FITMOS)" Int. Symp. on Power Sem Dev, 2005, pp. 43-46.
16. G. Koops et al., "Resurf Stepped Oxide (RSO) MOSFET for 85V Having a Record-Low Ron", Int. Symp. on Power Sem Dev, 2004, pp. 185-188.
17. L. Theolier et al., "Switching Perfomiance of 65V Vertical n-Channel FLYMOSFETs", Int. Symp. on Power Sem., 2006, pp. 117-122.
18. F. De Pestel et al., "Development of a Robust 50V 0.35 um Based Smart Power Technology Using Trench Isolation", Int. Symp. on Power Sem. Dev., 2003, pp. 182-185.
19. M.G.L. van den Heuvel et al., "An Improved Method for Determining the Inversion Layer Mobility of Electrons in Trench MOSFETs", Int. Symp. om Power Sem Dev, 2003, pp. 173-177.