Development of a robust 50V 0.35 μm based smart power technology using trench isolation

IEEE International Symposium on Power Semiconductor Devices and ICs (ISPSD)

Volumn , Issue , 2003, Pages 182-185

  De Pestel, F ^a   Moens, P ^a   Hakim, H ^a   De Vleeschouwer, H ^a   Reynders, K ^a   Colpaert, T ^a   Colson, P ^a   Coppens, P ^a   Boonen, S ^a   Bolognesi, D ^a   Tack, M ^a  

^a Technology Research and Development   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR TRANSISTORS; CAPACITORS; INTERFACES (MATERIALS); SEMICONDUCTOR JUNCTIONS;

SMART POWER TECHNOLOGY;

CMOS INTEGRATED CIRCUITS;

EID: 0042440611     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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2. Patent nr 02290902.2 (2002)
3. 2 Resurf LDMOS in a 0.35 μm CMOS Process.", Proceedings of the ISPSD 2000 Symposium (2000), pp 335-338.
4. A. Moscatelli, A. Merlini, G. Groce, P. Galbiati, C. Contiero, "LDMOS Implementation in a 0.35 μm BCD Technology (BCD6).", Proceedings of the ISPSD 2000 Symposium (2000), pp 323-326.
5. E. de Fresart, R. De Souza, J. Morrison, P. Parris, J. Heddleson, V. Venkatesan, W. Paulson, D. Collins, G. Nivison, B. Baumert, W. Cowden, D. Blomberg, "Integration of Multi-Voltage Analog and Power Devices in a 0.25 μm CMOS + Flash Memory Process.", Proceedings of the ISPSD 2002 Symposium (2002), pp 305-308.
6. V. Parthasarathy, R. Zhu, V. Khemka, T. Roggenbauer, A. Bose, P. Hui, P. Rodriquez, J. Nivison, D. Collins, Z. Wu, I. Puchades, M. Butner, "A 0.25 μm CMOS based 70V smart power technology with deep trench for highvoltage isolation.", Proceedings of the IEDM meeting (2002), pp 459-462.
7. P. Moens, G. Van den Bosch, G. Groeseneken, D. Bolognesi, "A Unified Hot Carrier Degradation Model for Integrated Lateral and Vertical nDMOS Transistors.", Proceedings of the ISPSD2003 Symposium (2003).