Temperature characteristics of a new 100V rated power MOSFET, VLMOS (Vertical LOCOS MOS)

IEEE International Symposium on Power Semiconductor Devices and ICs (ISPSD)

Volumn 16, Issue , 2004, Pages 463-466

  Kodama, Masahito ^a   Hayashi, Eiko ^a   Nishibe, Yuji ^a   Uesugi, Tsutomu ^a  

^a Rd Management Section   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC BATTERIES; ELECTRIC INSULATORS; ELECTRIC RESISTANCE; HIGH TEMPERATURE EFFECTS; MOS DEVICES; OXIDATION; SILICON;

DRIFT REGION; IMPURITY CONCENTRATION; SUPER JUNCTION TECHNOLOGY; TRENCH GATES;

MOSFET DEVICES;

EID: 4944249633     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/wct.2004.239756     Document Type: Conference Paper

References (3)

1. G. Deboy et'al, "A new generation of high voltage MOSFETs breaks the limit line of silicon", Proc. IEDM, pp.683-685 (1998)
2. T. Nitta et'al, "Experimental Results and Simulation Analysis of 250V Super Trench Power MOSFET (STM)", Proc. ISPSD, pp.77-80, (2000)
3. T. Fujihira, "Theory of Semiconductor Superjunction Devices", Jpn. J. Appl. Phys., vol.36, pp.6254-6262 (1997)