Mapping a class of dependence algorithms to coarse-grained reconfigurable arrays: architectural parameters and methodology

International Journal of Embedded Systems

Volumn 2, Issue 1-2, 2006, Pages 114-127

  Hannig, Frank ^a   Dutta, Hritam ^a   Teich, Jürgen ^a  

^a UNIVERSITY OF ERLANGEN NUREMBERG   (Germany)

Author keywords

coarse grained reconfigurable architectures; mapping methodology; processor array

Indexed keywords

EID: 38549135754     PISSN: 17411068     EISSN: 17411076     Source Type: Journal    
DOI: 10.1504/ijes.2006.010170     Document Type: Article

References (51)

1. Baumgarte, V., Ehlers, G., May, F., Nückel, A., Vorbach, M. and Weinhardt, M. (2003) ‘PACT XPP – a self-reconfigurable data processing architecture’, The Journal of Supercomputing, Vol. 26, No. 2, pp.167–184.
2. Bednara, M. and Teich, J. (2001) ‘Synthesis of FPGA implementations from loop algorithms’, First International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA'01), Las Vegas, NV, June, pp.1–7.
3. Bednara, M. and Teich, J. (2003) ‘Automatic synthesis of FPGA processor arrays from loop algorithms’, The Journal of Supercomputing, Vol. 26, No. 2, pp.149–165.
4. Bednara, M., Hannig, F. and Teich, J. (2001) ‘Boundary control: a new distributed control architecture for Space-Time Transformed (VLSI) processor arrays’, Proceedings 35th IEEE Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, USA, November.
5. Bednara, M., Hannig, F. and Teich, J. (2002) ‘Generation of distributed loop control’, in Deprettere, E., Teich, J. and Vassiliadis, S. (Eds.): Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation – SAMOS, Ser. Lecture Notes in Computer Science (LNCS), Heidelberg, Germany: Springer, Vol. 2268, pp.154–170.
6. DeHon, A. (1996) ‘Reconfigurable architectures for general-purpose computing’, MIT AI Lab, Massachusetts, Tech. Rep. A.I. TR No. 1586.
7. Dutta, H., Hannig, F. and Teich, J. (2006a) ‘Mapping of nested loop programs onto massively parallel processor arrays with memory and I/O constraints’, in Meyer auf der Heide, F. and Monien, B. (Eds.): Proceedings of the 6th International Heinz Nixdorf Symposium, New Trends in Parallel & Distributed Computing, Vol. 181 of HNI-Verlagsschriftenreihe, Paderborn, Germany, January, pp.97–119.
8. Dutta, H., Hannig, F. and Teich, J. (2006b) ‘Controller synthesis for mapping partitioned programs on array architectures’, Proceedings of the 19th International Conference on Architecture of Computing Systems (ARCS 2006), Frankfurt/Main, Germany, March, pp.176–191.
9. Eckhardt, U. and Merker, R. (1999) ‘Hierarchical algorithm partitioning at system level for an improved utilization of memory structures’, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 18, No. 1, pp.14–24.
10. Feautrier, P. (1996) Automatic Parallelization in the Polytope Model, Laboratoire PRiSM, Universite des Versailles St-Quentin en Yvelines, 45, avenue des Etats-Unis, F-78035 Versailles Cedex, Tech. Rep. 8, June.
11. Gunnarsson, F., Hansson, C., Johnsson, D. and Svensson, B. (2002) ‘Implementing high speed matrix processing on a reconfigurable parallel dataflow processor’, Second International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA'02), Las Vegas, NV, June, pp.74–80.
12. Gupta, S., Dutt, N., Gupta, R. and Nicolau, A. (2003) ‘SPARK: a high-level synthesis framework for applying parallelizing compiler transformations’, Proceedings of the International Conference on VLSI Design, January.
13. Hannig, F. and Teich, J. (2001) ‘Design space exploration for massively parallel processor arrays’, in Malyshkin, V. (Ed.): Parallel Computing Technologies, 6th International Conference, PaCT2001, Proceedings, Ser. Lecture Notes in Computer Science (LNCS), Springer, Novosibirsk, Russia, Vol. 2127, September, pp.51–65.
14. Hannig, F. and Teich, J. (2002) ‘Energy estimation of nested loop programs’, Proceedings 14th Annual ACM Symposium on Parallel Algorithms and Architectures (SPAA 2002), ACM Press, Winnipeg, Manitoba, Canada, August.
15. Hannig, F. and Teich, J. (2004a) Domain-Specific Processors: Systems, Architectures, Modeling, and Simulation, ser. Signal Processing and Communications, Marcel Dekker, New York, USA, No. 20, Ch. 6, Energy Estimation and Optimization for Piecewise Regular Processor Arrays, pp.107–126.
16. Hannig, F. and Teich, J. (2004b) ‘Dynamic piecewise linear/regular algorithms’, Proceedings of the Fourth International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004), Dresden, Germany, September, pp.79–84.
17. Hannig, F. and Teich, J. (2004c) ‘Resource constrained and speculative scheduling of an algorithm class with run-time dependent conditionals’, Proceedings IEEE 15th International Conference on Application-specific Systems, Architectures and Processors (ASAP 2004), Galveston, TX, USA, September, pp.17–27.
18. Hannig, F. and Teich, J. (2005) ‘Output serialization for FPGA-based and coarse-grained processor arrays’, Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), Las Vegas, NV, USA, June, pp.78–84.
19. Hannig, F., Dutta, H., Kupriyanov, A., Teich, J., Schaffer, R., Siegel, S., Merker, R., Keryell, R., Pottier, B., Chillet, D., Ménard, D. and Sentieys, O. (2005) ‘Co-design of massively parallel embedded processor architectures’, Proceedings of the first ReCoSoC Workshop, Montpellier, France, June.
20. Hartenstein, R. (2001) ‘A decade of reconfigurable computing: a visionary retrospective’, Proceedings of Design, Automation and Test in Europe, IEEE Computer Society, March, Munich, Germany, pp.642–649.
21. Karp, R., Miller, R. and Winograd, S. (1967) ‘The organization of computations for uniform recurrence equations’, Journal of the Association for Computing Machinery, Vol. 14, No. 3, pp.563–590.
22. Kathail, V., Aditya, S., Schreiber, R., Rau, B.R., Cronquist, D.C. and Sivaraman, M. (2002) ‘PICO: automatically designing custom computers’, Computer, Vol. 35, No. 9, pp.39–47.
23. Kienhuis, B., Rijpkema, E. and Deprettere, E. (2000) ‘Compaan: deriving process networks from Matlab for embedded signal processing architectures’, Proceedings of the 8th International Workshop on Hardware/Software Co-Design, ACM Press, pp.13–17.
24. Kuhn, R. (1980) ‘Transforming algorithms for single-stage and VLSI architectures’, Workshop on Interconnection Networks for Parallel and Distributed Processing, West Layfaette, IN, April, pp.11–19.
25. Lee, J., Choi, K. and Dutt, N. (2003) ‘An algorithm for mapping loops onto coarse-grained reconfigurable architectures’, Languages, Compilers, and Tools for Embedded Systems (LCTES'03), ACM Press, San Diego, CA, June, pp. 183–188.
26. Li, Y., Callahan, T., Darnell, E., Harr, R., Kurkure, U. and Stockwood, J. (2000) ‘Hardware-software co-design of embedded reconfigurable architectures’, 37th Design Automation Conference, Los Angeles, CA, June, pp.507–512.
27. Motomura, M. (2002) ‘A dynamically reconfigurable processor architecture’, Microprocessor Forum, CA.
28. Oldfield, J. and Dorf, R. (1995) Field Programmable Gate Arrays: Reconfigurable Logic for Rapid Prototyping and Implementation of Digital Systems, John Wiley & Sons, Chichester, New York.
29. PACT XPP Technologies (2003) XPP64-A1 Reconfigurable Processor -Datasheet, Munich, Germany.
30. Rao, S. (1985) Regular Iterative Algorithms and their Implementations on Processor Arrays, PhD Dissertation, Stanford University, CA, USA.
31. Schaumont, P., Verbauwhede, I., Keutzer, K. and Sarrafzadeh, M. (2001) ‘A quick safari through the reconfiguration jungle’, 38th Design Automation Conference, Las Vegas, NV, June, pp.172–177.
32. Schreiber, R., Aditya, S., Rau, B., Kathail, V., Mahlke, S., Abraham, S. and Snider, G. (2000) High-Level Synthesis of Nonprogrammable Hardware Accelerators, Hewlett-Packard Laboratories, Palo Alto, Tech. Rep. HPL-2000-31, May.
33. Singh, H., Lee, M-H., Lu, G., Bagherzadeh, N., Kurdahi, F.J. and Filho, E.M.C. (2000) ‘Morphosys: an integrated reconfigurable system for data-parallel and computation-intensive applications’, IEEE Transactions on Computers, Vol. 49, No. 5, pp.465–481.
34. Teich, J. (1993) A Compiler for Application-Specific Processor Arrays, PhD Dissertation, Institut fur Mikroelektronik, Universitat des Saarlandes, Saarbrücken, Deutschland.
35. Teich, J. and Thiele, L. (1991) ‘Control generation in the design of processor arrays’, Int. Journal on VLSI and Signal Processing, Vol. 3, No. 2, pp.77–92.
36. Teich, J. and Thiele, L. (1993) ‘Partitioning of processor arrays: a piecewise regular approach’, INTEGRATION: The VLSI Journal, Vol. 14, No. 3, pp.297–332.
37. Teich, J. and Thiele, L. (2002) ‘Exact partitioning of affine dependence algorithms’, in Deprettere, E., Teich, J. and Vassiliadis, S. (Eds.): Embedded Processor Design Challenges, ser. Lecture Notes in Computer Science (LNCS), Vol. 2268, March, pp.135–153.
38. Teich, J., Thiele, L. and Zhang, L. (1997) ‘Scheduling of partitioned regular algorithms on processor arrays with constrained resources’, Journal of VLSI Signal Processing, Vol. 17, No. 1, September, pp.5–20.
39. Thiele, L. (1992) Computer Systems and Software Engineering: State-of-the-Art, Kluwer Academic Publishers, Boston, USA, Ch. 4, Compiler Techniques for Massive Parallel Architectures, pp.101–151.
40. Thiele, L. (1995) ‘Resource constrained scheduling of uniform algorithms’, Journal of VLSI Signal Processing, Vol. 10, pp.295–310.
41. Venkataramani, G., Najjar, W., Kurdahi, F., Bagherzadeh, N., Bohm, W. and Hammes, J. (2003) ‘Automatic compilation to a coarse-grained reconfigurable system-on-chip’, ACM Trans. on Embedded Computing Systems, November.
42. Weinhardt, M. and Luk, W. (2001) ‘Pipeline vectorization’, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 20, February, pp.234–248.
43. Wilde, D. and Sie, O. (1994) ‘Regular array synthesis using alpha’, Int. Conf. on Application Specific Array Processors, San Francsico, California, August, pp.200–211.
44. CELOXICA, Handel-C, ‘www.celoxica.com’.
45. Elixent Ltd., ‘www.elixent.com’.
46. PARO Design System Project, ‘www12.cs.fau.de/research/paro’.
47. QuickSilver Technology, ‘www.qstech.com’.
48. Silicon Hive, ‘www.siliconhive.com’.
49. Synfora, Inc., ‘www.synfora.com’.
50. A vector x is said to be coprime if the absolute value of the greatest value of the greatest common divisor of its elements is one.
51. Note, that the iteration space is shifted for each iteration variable by one.