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Volumn 2127, Issue , 2001, Pages 51-65

Design space exploration for massively parallel processor arrays

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION THEORY; COSTS; HARDWARE; INTEGRATED CIRCUIT DESIGN; MAPPING; SYSTEMS ANALYSIS;

EID: 84937567590     PISSN: None     EISSN: None     Source Type: Journal    
DOI: 10.1007/3-540-44743-1_5     Document Type: Article
Times cited : (25)

References (16)
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    • Philadelphia, Pennsylvania, May
    • Philippe Clauss. Counting Solutions to Linear and Nonlinear Constraints through Ehrhart polynomials: Applications to Analyse and Transform Scientific Programs. In Tenth ACM International Conference on Supercomputing, Philadelphia, Pennsylvania, May 1996
    • Tenth ACM International Conference on Supercomputing , pp. 1996
    • Clauss, P.1
  • 2
    • 0032117761 scopus 로고    scopus 로고
    • Parametric Analysis of Polyhedral Iteration Spaces
    • Philippe Clauss and Vincent Loechner. Parametric Analysis of Polyhedral Iteration Spaces. Journal of VLSI Signal Processing, 19(2):179-194, July 1998
    • (1998) Journal of VLSI Signal Processing , vol.19 , Issue.2 , pp. 179-194
    • Clauss, P.1    Loechner, V.2
  • 3
    • 0041177670 scopus 로고    scopus 로고
    • Determination of Processor Allocation in the Design of Processor Arrays
    • Dirk Fimmel and Renate Merker. Determination of Processor Allocation in the Design of Processor Arrays. Microprocessors and Microsystems, 22(3-4):149-155, 1998
    • (1998) Microprocessors and Microsystems , vol.22 , Issue.3-4 , pp. 149-155
    • Fimmel, D.1    Merker, R.2
  • 6
    • 85029516676 scopus 로고
    • Loop Parallelization in the Polytope Model
    • ike Best, editor, CONCUR’93, Springer-Verlag
    • Christian Lengauer. Loop Parallelization in the Polytope Model. In Eike Best, editor, CONCUR’93, Lecture Notes in Computer Science 715, pages 398-416. Springer-Verlag, 1993
    • (1993) Lecture Notes in Computer Science , vol.715 , pp. 398-416
    • Lengauer, C.1
  • 7
    • 0020589597 scopus 로고
    • On the Design of Algorithms for VLSI Systolic Arrays
    • Dan I. Moldovan. On the Design of Algorithms for VLSI Systolic Arrays. In Proceedings of the IEEE, volume 71, pages 113-120, January 1983
    • (1983) Proceedings of the IEEE , vol.71 , pp. 113-120
    • Moldovan, D.I.1
  • 9
    • 85016923187 scopus 로고
    • F. Rouge & Cie., Lausanne, Switzerland
    • Vilfredo Pareto. Cours d’Economie Politique, volume 1. F. Rouge & Cie., Lausanne, Switzerland, 1896
    • (1896) Cours d’Economie Politique , vol.1
    • Pareto, V.1
  • 12
    • 0006436941 scopus 로고
    • PhD thesis, Institut für Mikroelektronik, Universität des Saarlandes, Saarbrücken, Germany
    • Jürgen Teich. A Compiler for Application-Specific Processor Arrays. PhD thesis, Institut für Mikroelektronik, Universität des Saarlandes, Saarbrücken, Germany, 1993
    • (1993) A Compiler for Application-Specific Processor Arrays
    • Teich, J.1
  • 13
    • 0031221084 scopus 로고    scopus 로고
    • Scheduling of Partitioned Regular Algorithms on Processor Arrays with Constrained Resources
    • Jürgen Teich, Lothar Thiele, and Li Zhang. Scheduling of Partitioned Regular Algorithms on Processor Arrays with Constrained Resources. Journal of VLSI Signal Processing, 17(1):5-20, September 1997
    • (1997) Journal of VLSI Signal Processing , vol.17 , Issue.1 , pp. 5-20
    • Teich, J.1    Thiele, L.2    Li, Z.3
  • 14
    • 0029349837 scopus 로고
    • Resource Constrained Scheduling of Uniform Algorithms
    • Lothar Thiele. Resource Constrained Scheduling of Uniform Algorithms. Journal of VLSI Signal Processing, 10:295-310, 1995
    • (1995) Journal of VLSI Signal Processing , vol.10 , pp. 295-310
    • Thiele, L.1
  • 15
    • 0040426720 scopus 로고
    • Technical Report YALEEU/DCS/RR-697, Yale University, Department of Computer Science, New Haven, Conneticut
    • Yiwan Wong and Jean-Marc Delosme. Optimization of Processor Count for Systolic Arrays. Technical Report YALEEU/DCS/RR-697, Yale University, Department of Computer Science, New Haven, Conneticut, 1989
    • (1989) Optimization of Processor Count for Systolic Arrays
    • Wong, Y.1    Delosme, J.-M.2
  • 16
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    • Xilinx, Inc
    • Xilinx, Inc. http://www.xilinx.com/products/software/jbits/


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.