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Volumn 2268, Issue , 2002, Pages 154-170

Generation of distributed loop control

Author keywords

[No Author keywords available]

Indexed keywords

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 24644443395     PISSN: 03029743     EISSN: 16113349     Source Type: Journal    
DOI: 10.1007/3-540-45874-3_9     Document Type: Article
Times cited : (6)

References (21)
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    • Philippe Clauss and Vincent Loechner. Parametric Analysis of Polyhedral Iteration Spaces. Journal of VLSI Signal Processing, 19(2):179-194, July 1998.
    • (1998) Journal of VLSI Signal Processing , vol.19 , Issue.2 , pp. 179-194
    • Clauss, P.1    Loechner, V.2
  • 9
    • 0003859414 scopus 로고
    • Prentice Hall, Englewood Cliffs, New Jersey
    • Sun Yuan Kung. VLSI Array Processors. Prentice Hall, Englewood Cliffs, New Jersey, 1987.
    • (1987) VLSI Array Processors
    • Kung, S.Y.1
  • 11
    • 0020589597 scopus 로고
    • Moldovan. On the Design of Algorithms for VLSI Systolic Arrays
    • January
    • Dan I. Moldovan. On the Design of Algorithms for VLSI Systolic Arrays. In Proceedings of the IEEE, volume 71, pages 113-120, January 1983.
    • (1983) Proceedings of the IEEE , vol.71 , pp. 113-120
    • Dan, I.1
  • 12
    • 0003690189 scopus 로고
    • Theory of Linear and Integer Programming
    • John Wiley and Sons, Chichester, New York
    • Alexander Schrijver. Theory of Linear and Integer Programming. Whily-Interscience series in discrete mathematics. John Wiley and Sons, Chichester, New York, 1986.
    • (1986) Whily-Interscience Series in Discrete Mathematics
    • Schrijver, A.1
  • 14
    • 0026171253 scopus 로고
    • Control Generation in the Design of Processor Arrays
    • Jürgen Teich and Lothar Thiele. Control Generation in the Design of Processor Arrays. Int. Journal on VLSI and Signal Processing, 3(2):77-92, 1991.
    • (1991) Int. Journal on VLSI and Signal Processing , vol.3 , Issue.2 , pp. 77-92
    • Teich, J.1    Thiele, L.2
  • 15
    • 0006397826 scopus 로고
    • Control Generation in the Design of Processor Arrays
    • Josef A. Nossek, editor, Kluwer Academic Publishers
    • Jürgen Teich and Lothar Thiele. Control Generation in the Design of Processor Arrays. In Josef A. Nossek, editor, Parallel Processing on VLSI Arrays. Kluwer Academic Publishers, 1992.
    • (1992) Parallel Processing on VLSI Arrays
    • Teich, J.1    Thiele, L.2
  • 16
    • 0027541568 scopus 로고
    • Partitioning of Processor Arrays: A Piecewise Regular Approach
    • Jürgen Teich and Lothar Thiele. Partitioning of Processor Arrays: A Piecewise Regular Approach. INTEGRATION: The VLSI Journal, 14(3):297-332, 1993.
    • (1993) INTEGRATION: The VLSI Journal , vol.14 , Issue.3 , pp. 297-332
    • Teich, J.1    Thiele, L.2
  • 17
    • 0024888925 scopus 로고
    • On the Design of Piecewise Regular Processor Arrays
    • Portland
    • Lothar Thiele. On the Design of Piecewise Regular Processor Arrays. In Proc. IEEE Symp. on Circuits and Systems, pages 2239-2242, Portland, 1989.
    • (1989) Proc. IEEE Symp. On Circuits and Systems , pp. 2239-2242
    • Thiele, L.1
  • 18
    • 0029349837 scopus 로고
    • Scheduling of Uniform Algorithms with Resource Constraints
    • Lothar Thiele. Scheduling of Uniform Algorithms with Resource Constraints. Journal of VLSI Signal Processing, 10:295-310, 1995.
    • (1995) Journal of VLSI Signal Processing , vol.10 , pp. 295-310
    • Thiele, L.1
  • 20
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    • Xilinx Inc. http://www.xilinx.com/partinfo/ds003-2.pdf.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.