-
3
-
-
0032117761
-
Parametric Analysis of Polyhedral Iteration Spaces
-
Philippe Clauss and Vincent Loechner. Parametric Analysis of Polyhedral Iteration Spaces. Journal of VLSI Signal Processing, 19(2):179-194, July 1998.
-
(1998)
Journal of VLSI Signal Processing
, vol.19
, Issue.2
, pp. 179-194
-
-
Clauss, P.1
Loechner, V.2
-
4
-
-
0002352131
-
Linear Scheduling is Nearly Optimal
-
Alain Darte, Leonid Khachiyan, and Yves Robert. Linear Scheduling is Nearly Optimal. Parallel Processing Letters, 1(2):73-81, 1991.
-
(1991)
Parallel Processing Letters
, vol.1
, Issue.2
, pp. 73-81
-
-
Darte, A.1
Khachiyan, L.2
Robert, Y.3
-
6
-
-
84937567590
-
Design Space Exploration for Massively Parallel Processor Arrays
-
Victor Malyshkin, editor, Novosibirsk, Russia, September, Springer
-
Frank Hannig and Jürgen Teich. Design Space Exploration for Massively Parallel Processor Arrays. In Victor Malyshkin, editor, Parallel Computing Technologies, 6th International Conference, PaCT 2001, Proceedings, volume 2127 of Lecture Notes in Computer Science (LNCS), pages 51-65, Novosibirsk, Russia, September 2001. Springer.
-
(2001)
Parallel Computing Technologies, 6Th International Conference, Pact 2001, Proceedings, Volume 2127 of Lecture Notes in Computer Science (LNCS)
, pp. 51-65
-
-
Hannig, F.1
Teich, J.2
-
7
-
-
0001512318
-
The Organization of Computations for Uniform Recurrence Equations
-
Richard M. Karp, Raymond E. Miller, and Shmuel Winograd. The Organization of Computations for Uniform Recurrence Equations. Journal of the Association for Computing Machinery, 14(3):563-590, 1967.
-
(1967)
Journal of the Association for Computing Machinery
, vol.14
, Issue.3
, pp. 563-590
-
-
Karp, R.M.1
Miller, R.E.2
Winograd, S.3
-
9
-
-
0003859414
-
-
Prentice Hall, Englewood Cliffs, New Jersey
-
Sun Yuan Kung. VLSI Array Processors. Prentice Hall, Englewood Cliffs, New Jersey, 1987.
-
(1987)
VLSI Array Processors
-
-
Kung, S.Y.1
-
10
-
-
85029516676
-
Loop Parallelization in the Polytope Model
-
Springer-Verlag
-
Christian Lengauer. Loop Parallelization in the Polytope Model. In Eike Best, editor, CONCUR’93, Lecture Notes in Computer Science 715, pages 398-416. Springer-Verlag, 1993.
-
(1993)
Eike Best, Editor, CONCUR’93, Lecture Notes in Computer Science 715
, pp. 398-416
-
-
Lengauer, C.1
-
11
-
-
0020589597
-
Moldovan. On the Design of Algorithms for VLSI Systolic Arrays
-
January
-
Dan I. Moldovan. On the Design of Algorithms for VLSI Systolic Arrays. In Proceedings of the IEEE, volume 71, pages 113-120, January 1983.
-
(1983)
Proceedings of the IEEE
, vol.71
, pp. 113-120
-
-
Dan, I.1
-
12
-
-
0003690189
-
Theory of Linear and Integer Programming
-
John Wiley and Sons, Chichester, New York
-
Alexander Schrijver. Theory of Linear and Integer Programming. Whily-Interscience series in discrete mathematics. John Wiley and Sons, Chichester, New York, 1986.
-
(1986)
Whily-Interscience Series in Discrete Mathematics
-
-
Schrijver, A.1
-
15
-
-
0006397826
-
Control Generation in the Design of Processor Arrays
-
Josef A. Nossek, editor, Kluwer Academic Publishers
-
Jürgen Teich and Lothar Thiele. Control Generation in the Design of Processor Arrays. In Josef A. Nossek, editor, Parallel Processing on VLSI Arrays. Kluwer Academic Publishers, 1992.
-
(1992)
Parallel Processing on VLSI Arrays
-
-
Teich, J.1
Thiele, L.2
-
16
-
-
0027541568
-
Partitioning of Processor Arrays: A Piecewise Regular Approach
-
Jürgen Teich and Lothar Thiele. Partitioning of Processor Arrays: A Piecewise Regular Approach. INTEGRATION: The VLSI Journal, 14(3):297-332, 1993.
-
(1993)
INTEGRATION: The VLSI Journal
, vol.14
, Issue.3
, pp. 297-332
-
-
Teich, J.1
Thiele, L.2
-
17
-
-
0024888925
-
On the Design of Piecewise Regular Processor Arrays
-
Portland
-
Lothar Thiele. On the Design of Piecewise Regular Processor Arrays. In Proc. IEEE Symp. on Circuits and Systems, pages 2239-2242, Portland, 1989.
-
(1989)
Proc. IEEE Symp. On Circuits and Systems
, pp. 2239-2242
-
-
Thiele, L.1
-
18
-
-
0029349837
-
Scheduling of Uniform Algorithms with Resource Constraints
-
Lothar Thiele. Scheduling of Uniform Algorithms with Resource Constraints. Journal of VLSI Signal Processing, 10:295-310, 1995.
-
(1995)
Journal of VLSI Signal Processing
, vol.10
, pp. 295-310
-
-
Thiele, L.1
-
20
-
-
85018981839
-
-
Xilinx Inc. http://www.xilinx.com/partinfo/ds003-2.pdf.
-
-
-
|