Dynamic piecewise linear/regular algorithms

International Conference on Parallel Computing in Electrical Engineering: Workshop on System Design Automation, SDA, PARELEC 2004

Volumn , Issue , 2004, Pages 79-84

  Hannig, Frank ^a   Teich, Jürgen ^a  

^a UNIVERSITY OF ERLANGEN NUREMBERG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CODES (SYMBOLS); COMPUTATIONAL METHODS; CONFORMAL MAPPING; ITERATIVE METHODS; LINEAR ALGEBRA; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; OPTIMIZATION; PARALLEL PROCESSING SYSTEMS; SCHEDULING; SEMANTICS; VECTORS;

AFFINE INDEXED ALGORITHMS (AIA); PIECEWISE REGULAR ALGORITHMS (PRA); PIECEWISW LINEAR ALGORITHMS (PLA); SINGLE ASSIGNMENT CODES (SAC);

PIECEWISE LINEAR TECHNIQUES;

EID: 13944278796     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (21)

1. M. Bednara and J. Teich. Synthesis of FPGA Implementations from Loop Algorithms. In First International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA'01), pages 1-7, Las Vegas, NV, June 2001.
2. M. Bednara and J. Teich. Automatic Synthesis of FPGA Processor Arrays from Loop Algorithms. The Journal of Supercomputing, 26(2):149-165, 2003.
3. O. S. D. Wilde. Regular Array Synthesis using Alpha. In Int. Conf. on Application Specific Array Processors, San Francsico, California, pages 200-211, Aug. 1994.
4. U. Eckhardt and R. Merker. Hierarchical Algorithm Partitioning at System Level for an Improved Utilization of Memory Structures. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 18(1): 14-24, 1999.
5. P. Feautrier. Automatic Parallelization in the Polytope Model. Technical Report 8, Laboratoire PRiSM, Université des Versailles St-Quentin en Yvelines, 45, avenue des États-Unis, F-78035 Versailles Cedex, June 1996.
6. M. Griebl and C. Lengauer. The loop parallelizer LooPo. In M. Gerndt, editor, Proc. Sixth Workshop on Compilers for Parallel Computers, volume 21 of Konferenzen des Forschungszentrums Jülich, pages 311-320. Forschungszentrum Jülich, 1996.
7. S. Gupta, N. Dutt, R. Gupta, and A. Nicolau. Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow. In G. Gielen and J. Figueras, editors, Proceedings of Design, Automation and Test in Europe, pages 114-119, Paris, France, Feb. 2004. IEEE Computer Society.
8. F. Hannig, H. Dutta, and J. Teich. Regular Mapping for Coarse-grained Reconfigurable Architectures. In Proceedings of the 2004 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2004), Montreal, Quebec, Canada, May 2004.
9. F. Hannig and J. Teich. Design Space Exploration for Massively Parallel Processor Arrays. In V. Malyshkin, editor, Parallel Computing Technologies, 6th International Conference, PaCT 2001, Proceedings, volume 2127 of Lecture Notes in Computer Science (LNCS), pages 51-65, Novosibirsk, Russia, Sept. 2001. Springer.
10. F. Hannig and J. Teich. Regular Dynamic Dependence Algorithms - Definition and Resource Constrained Scheduling. Submitted to IEEE 15th International Conference on Application-specific Systems, Architectures and Processors (ASAP 2004), Galveston, TX, U.S.A., Sept. 2004.
11. R. Karp, R. Miller, and S. Winograd. The Organization of Computations for Uniform Recurrence Equations. Journal of the Association for Computing Machinery, 14(3):563-590, 1967.
12. V. Kathail, S. Aditya, R. Schreiber, B. R. Rau, D. C. Cronquist, and M. Sivaraman. PICO: Automatically Designing Custom Computers. Computer, 35(9):39-47, 2002.
13. B. Kienhuis. MatParser: An Array Dataflow Analysis Compiler. Technical Report UCB/ERL M00/9, University of California, Berkeley, CA-94720, U.S.A., Feb. 2000.
14. B. Kienhuis, E. Rijpkema, and E. Deprettere. Compaan: Deriving Process Networks from Matlab for Embedded Signal Processing Architectures. In Proceedings of the eighth international workshop on Hardware/software codesign, pages 13-17. ACM Press, 2000.
15. PARO Design System Project. www12. Informatik.unierlangen.de/research/ paro.
16. S. Rao. Regular Iterative Algorithms and their Implementations on Processor Arrays. PhD thesis, Stanford University, 1985.
17. R. Schreiber, S. Aditya, B. Rau, V. Kathail, S. Mahlke, S. Abraham, and G. Snider. High-Level Synthesis of Non-programmable Hardware Accelerators. Technical Report HPL-2000-31, Hewlett-Packard Laboratories, Palo Alto, May 2000.
18. Synfora, Inc. www.synfora.com.
19. J. Teich. A Compiler for Application-Specific Processor Arrays. PhD thesis, Institut für Mikroelektronik, Universität des Saarlandes, Saarbrücken, Deutschland, 1993.
20. L. Thiele. Computer Systems and Software Engineering: State-of-the-Art, chapter 4, Compiler Techniques for Massive Parallel Architectures, pages 101-151. Kluwer Academic Publishers, Boston, U.S.A., 1992.
21. L. Thiele. Resource Constrained Scheduling of Uniform Algorithms. Journal of VLSI Signal Processing, 10:295-310, 1995.