Automatic synthesis of FPGA processor arrays from loop algorithms

Journal of Supercomputing

Volumn 26, Issue 2, 2003, Pages 149-165

  Bednara, Marcus ^a   Teich, Jürgen ^a  

^a UNIVERSITY OF PADERBORN   (Germany)

Author keywords

Design automation; FPGA; Regular processor arrays; Space time mapping

Indexed keywords

ALGORITHMS; COMPUTER HARDWARE; COMPUTER HARDWARE DESCRIPTION LANGUAGES; HIGH LEVEL LANGUAGES; INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN; MICROPROCESSOR CHIPS; OPTIMIZATION; PARALLEL PROCESSING SYSTEMS; VLSI CIRCUITS;

AUTOMATIC SYNTHESIS; DESIGN AUTOMATION; REGULAR PROCESSOR ARRAYS; SPACE TIME MAPPING;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0042022007     PISSN: 09208542     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1024447517501     Document Type: Article

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