메뉴 건너뛰기




Volumn 3894 LNCS, Issue , 2006, Pages 176-190

Controller synthesis for mapping partitioned programs on array architectures

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CACHE MEMORY; COMPUTER SOFTWARE; CONTROL SYSTEMS; MAPPING; PROGRAM PROCESSORS; SCHEDULING;

EID: 33745618958     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/11682127_13     Document Type: Conference Paper
Times cited : (9)

References (20)
  • 1
    • 33745608757 scopus 로고    scopus 로고
    • Synfora, Inc.: (www.synfora.com)
  • 2
    • 33745600592 scopus 로고    scopus 로고
    • Interfacing compiled FPGA programs: The MMAlpha approach
    • Derrien, S., Risset, T.: Interfacing Compiled FPGA Programs: The MMAlpha Approach. In: PDPTA. (2000)
    • (2000) PDPTA
    • Derrien, S.1    Risset, T.2
  • 3
    • 85029516676 scopus 로고
    • Loop parallelization in the polytope model
    • Best, E., ed.: CONCUR'93., Springer-Verlag
    • Lengauer, C.: Loop Parallelization in the Polytope Model. In Best, E., ed.: CONCUR'93. Lecture Notes in Computer Science 715, Springer-Verlag (1993) 398-416
    • (1993) Lecture Notes in Computer Science , vol.715 , pp. 398-416
    • Lengauer, C.1
  • 7
    • 0031221084 scopus 로고    scopus 로고
    • Scheduling of partitioned regular algorithms on processor arrays with constrained resources
    • Teich, J., Thiele, L., Zhang, L.: Scheduling of Partitioned Regular Algorithms on Processor Arrays with Constrained Resources. Journal of VLSI Signal Processing 17(1) (1997) 5-20
    • (1997) Journal of VLSI Signal Processing , vol.17 , Issue.1 , pp. 5-20
    • Teich, J.1    Thiele, L.2    Zhang, L.3
  • 12
    • 84949236166 scopus 로고    scopus 로고
    • Exact partitioning of affine dependence algorithms
    • Deprettere, E.F, Teich, J., Vassiliadis, S., eds.: Embedded Processor Design Challenges., Springer, Berlin
    • Teich, J., Thiele, L.: Exact Partitioning of Affine Dependence Algorithms. In Deprettere, E.F, Teich, J., Vassiliadis, S., eds.: Embedded Processor Design Challenges. Volume 2268 of Lecture Notes in Computer Science (LNCS)., Springer, Berlin (2002) 135-153
    • (2002) Lecture Notes in Computer Science (LNCS) , vol.2268 , pp. 135-153
    • Teich, J.1    Thiele, L.2
  • 13
    • 84937567590 scopus 로고    scopus 로고
    • Design space exploration for massively parallel processor arrays
    • Malyshkin, V., ed.: Parallel Computing Technologies, 6th International Conference, PaCT 2001, Proceedings., Novosibirsk, Russia, Springer
    • Hannig, F., Teich, J.: Design Space Exploration for Massively Parallel Processor Arrays. In Malyshkin, V., ed.: Parallel Computing Technologies, 6th International Conference, PaCT 2001, Proceedings. Volume 2127 of Lecture Notes in Computer Science (LNCS)., Novosibirsk, Russia, Springer (2001) 51-65
    • (2001) Lecture Notes in Computer Science (LNCS) , vol.2127 , pp. 51-65
    • Hannig, F.1    Teich, J.2
  • 14
    • 0003690189 scopus 로고
    • Wiley - Interscience series in discrete mathematics. John Wiley & Sons, Chichester, New York
    • Schrijver, A.: Theory of Linear and Integer Programming. Wiley - Interscience series in discrete mathematics. John Wiley & Sons, Chichester, New York (1986)
    • (1986) Theory of Linear and Integer Programming
    • Schrijver, A.1
  • 15
    • 33745633882 scopus 로고    scopus 로고
    • Control path generation for mapping partitioned dataflow-dominant algorithms onto array architectures
    • University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design
    • Dutta, F., Hannig, F., Teich, J.: Control Path Generation for Mapping Partitioned Dataflow-dominant Algorithms onto Array Architectures. Technical Report 03-2005, University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design (2005)
    • (2005) Technical Report , vol.3 , Issue.2005
    • Dutta, F.1    Hannig, F.2    Teich, J.3
  • 19
    • 38149022982 scopus 로고    scopus 로고
    • Hardware synthesis for multi-dimensional time
    • IEEE computer Society
    • Guillou, A., Quinton, P., Risset, T.: Hardware Synthesis for Multi-Dimensional Time,. IEEE computer Society, ASAP'2003 (2003)
    • (2003) ASAP'2003
    • Guillou, A.1    Quinton, P.2    Risset, T.3
  • 20
    • 33745617430 scopus 로고    scopus 로고
    • PARO Design System Project: (www12.informatik.uni-erlangen.de/research/ paro)


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.