-
1
-
-
33745608757
-
-
Synfora, Inc.: (www.synfora.com)
-
-
-
-
2
-
-
33745600592
-
Interfacing compiled FPGA programs: The MMAlpha approach
-
Derrien, S., Risset, T.: Interfacing Compiled FPGA Programs: The MMAlpha Approach. In: PDPTA. (2000)
-
(2000)
PDPTA
-
-
Derrien, S.1
Risset, T.2
-
3
-
-
85029516676
-
Loop parallelization in the polytope model
-
Best, E., ed.: CONCUR'93., Springer-Verlag
-
Lengauer, C.: Loop Parallelization in the Polytope Model. In Best, E., ed.: CONCUR'93. Lecture Notes in Computer Science 715, Springer-Verlag (1993) 398-416
-
(1993)
Lecture Notes in Computer Science
, vol.715
, pp. 398-416
-
-
Lengauer, C.1
-
6
-
-
0036005117
-
Constructing and exploiting linear schedules with prescribed parallelism
-
Darte, A., Schreiber, R., Rau, B., Vivien, F.: Constructing and Exploiting Linear Schedules with Prescribed Parallelism. ACM Transactions on Design Automation of Electronic Systems 7(1) (2002) 159-172
-
(2002)
ACM Transactions on Design Automation of Electronic Systems
, vol.7
, Issue.1
, pp. 159-172
-
-
Darte, A.1
Schreiber, R.2
Rau, B.3
Vivien, F.4
-
7
-
-
0031221084
-
Scheduling of partitioned regular algorithms on processor arrays with constrained resources
-
Teich, J., Thiele, L., Zhang, L.: Scheduling of Partitioned Regular Algorithms on Processor Arrays with Constrained Resources. Journal of VLSI Signal Processing 17(1) (1997) 5-20
-
(1997)
Journal of VLSI Signal Processing
, vol.17
, Issue.1
, pp. 5-20
-
-
Teich, J.1
Thiele, L.2
Zhang, L.3
-
8
-
-
4544332232
-
Regular mapping for coarse-grained reconfigurable architectures
-
Montréal, Quebec, Canada, IEEE Signal Processing Society
-
Hannig, F., Dutta, H., Teich, J.: Regular Mapping for Coarse-grained Reconfigurable Architectures. In: Proceedings of the 2004 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2004). Volume V., Montréal, Quebec, Canada, IEEE Signal Processing Society (2004) 57-60
-
(2004)
Proceedings of the 2004 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2004)
, vol.5
, pp. 57-60
-
-
Hannig, F.1
Dutta, H.2
Teich, J.3
-
12
-
-
84949236166
-
Exact partitioning of affine dependence algorithms
-
Deprettere, E.F, Teich, J., Vassiliadis, S., eds.: Embedded Processor Design Challenges., Springer, Berlin
-
Teich, J., Thiele, L.: Exact Partitioning of Affine Dependence Algorithms. In Deprettere, E.F, Teich, J., Vassiliadis, S., eds.: Embedded Processor Design Challenges. Volume 2268 of Lecture Notes in Computer Science (LNCS)., Springer, Berlin (2002) 135-153
-
(2002)
Lecture Notes in Computer Science (LNCS)
, vol.2268
, pp. 135-153
-
-
Teich, J.1
Thiele, L.2
-
13
-
-
84937567590
-
Design space exploration for massively parallel processor arrays
-
Malyshkin, V., ed.: Parallel Computing Technologies, 6th International Conference, PaCT 2001, Proceedings., Novosibirsk, Russia, Springer
-
Hannig, F., Teich, J.: Design Space Exploration for Massively Parallel Processor Arrays. In Malyshkin, V., ed.: Parallel Computing Technologies, 6th International Conference, PaCT 2001, Proceedings. Volume 2127 of Lecture Notes in Computer Science (LNCS)., Novosibirsk, Russia, Springer (2001) 51-65
-
(2001)
Lecture Notes in Computer Science (LNCS)
, vol.2127
, pp. 51-65
-
-
Hannig, F.1
Teich, J.2
-
14
-
-
0003690189
-
-
Wiley - Interscience series in discrete mathematics. John Wiley & Sons, Chichester, New York
-
Schrijver, A.: Theory of Linear and Integer Programming. Wiley - Interscience series in discrete mathematics. John Wiley & Sons, Chichester, New York (1986)
-
(1986)
Theory of Linear and Integer Programming
-
-
Schrijver, A.1
-
15
-
-
33745633882
-
Control path generation for mapping partitioned dataflow-dominant algorithms onto array architectures
-
University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design
-
Dutta, F., Hannig, F., Teich, J.: Control Path Generation for Mapping Partitioned Dataflow-dominant Algorithms onto Array Architectures. Technical Report 03-2005, University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design (2005)
-
(2005)
Technical Report
, vol.3
, Issue.2005
-
-
Dutta, F.1
Hannig, F.2
Teich, J.3
-
16
-
-
0034299275
-
Generation of efficient nested loops from polyhedra
-
Quillere, F., Rajopadhye, S., Wilde, D.: Generation of Efficient Nested Loops from Polyhedra. International Journal of Parallel Programming 28(5) (2000) 469-498
-
(2000)
International Journal of Parallel Programming
, vol.28
, Issue.5
, pp. 469-498
-
-
Quillere, F.1
Rajopadhye, S.2
Wilde, D.3
-
19
-
-
38149022982
-
Hardware synthesis for multi-dimensional time
-
IEEE computer Society
-
Guillou, A., Quinton, P., Risset, T.: Hardware Synthesis for Multi-Dimensional Time,. IEEE computer Society, ASAP'2003 (2003)
-
(2003)
ASAP'2003
-
-
Guillou, A.1
Quinton, P.2
Risset, T.3
-
20
-
-
33745617430
-
-
PARO Design System Project: (www12.informatik.uni-erlangen.de/research/ paro)
-
-
-
|