Device design and optimization methodology for leakage and variability reduction in sub-45-nm FD/SOI SRAM

IEEE Transactions on Electron Devices

Volumn 55, Issue 1, 2008, Pages 152-162

  Mukhopadhyay, Saibal ^a,b   Kim, Keunwoo ^a   Chuang, Ching Te ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Buried oxide (BOX); Fully depleted silicon on insulator (FD SOI); Leakage; Random dopant fluctuation (RDF); Read current; SRAM; Stability

Indexed keywords

LEAKAGE CURRENTS; OPTIMIZATION; SEMICONDUCTOR DOPING; SILICON ON INSULATOR TECHNOLOGY; THRESHOLD VOLTAGE;

BURIED OXIDE (BOX); FULLY-DEPLETED SILICON-ON-INSULATOR (FD/SOI); POWER MANAGEMENT; RANDOM DOPANT FLUCTUATION (RDF);

STATIC RANDOM ACCESS STORAGE;

EID: 37749022070     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2007.911073     Document Type: Article

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