Optimal UTB FD/SOI device structure using thin BOX for sub-50-nm SRAM design

IEEE Electron Device Letters

Volumn 27, Issue 4, 2006, Pages 284-287

  Mukhopadhyay, Saibal ^a   Kim, Keunwoo ^b   Wang, Xinlin ^b   Frank, David J ^b   Oldiges, Philip ^b   Chuang, Ching Te ^b   Roy, Kaushik ^a  

^a Purdue University   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Fully depleted silicon on insulator (SOI); Leakage; Performance; Random dopant fluctuations (RDFs); Stability; Static random access memory (SRAM)

Indexed keywords

PERFORMANCE; STATIC RANDOM ACCESS STORAGE; THRESHOLD VOLTAGE; ULTRATHIN FILMS;

FULLY DEPLETED SILICON-ON-INSULATOR; RANDOM DOPANT FLUCTUATIONS; THINNER BURIED OXIDE;

SILICON ON INSULATOR TECHNOLOGY;

EID: 33645643820     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2006.871540     Document Type: Article

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