SRAM circuit with expanded operating margin and reduced stand-by leakage current using thin-BOX FD-SOI transistors

2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005

Volumn , Issue , 2005, Pages 109-112

  Yamaoka, Masanao ^a   Tsuchiya, Ryuta ^a   Kawahara, Takayuki ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL CIRCUITS; ELECTRIC NETWORK ANALYSIS; LEAKAGE CURRENTS; STANDBY POWER SERVICE; TRANSISTORS;

FD-SOI; OPERATING MARGIN; SUPPLY VOLTAGE; THINBOX;

STATIC RANDOM ACCESS STORAGE;

EID: 34250744651     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2005.251677     Document Type: Conference Paper

References (5)

1. E. Seevinck et al., "Static-Noise Margin analysis of MOS SRAM cells," JSSC, Vol. 22, Issues 5, pp. 747-754, Oct. 1987.
2. R. Tsuchiya et al., "Silicon on Thin BOX: A New Paradigm of The CMOSFET for Low-Power and High-Performance Application Featuring Wide-Range Back-Bias Control," IEDM, 2004, pp. 631-634.
3. M. Yamaoka et al., "Low-Power Embedded SRAM Modules with Expanding Margins for Writing," ISSCC, Feb. 2005, pp. 480-481.
4. M. Yamaoka et al., "Low Power SRAM Menu for SOC Application Using Yin-Yang-Feedback Memory Cell Technology," VLSI Circuits, June 2004, pp. 288-291.
5. M. Yamaoka et al., "A 300MHz 25μA/Mb Leakage On-Chip SRAM Module Featuring Process-Variation Immunity and Low-Leakage-Active Mode for Mobile-Phone Application Processor," ISSCC, Feb. 2004, pp. 494-495.