DfT for the reuse of networks-on-chip as test access mechanism

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2007, Pages 435-440

  Amory, Alexandre M ^a   Ferlini, Frederico ^b   Lubaszewski, Marcelo ^a   Moraes, Fernando ^b  

^a FEDERAL UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

^b PONTIFICAL CATHOLIC UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

Author keywords

[No Author keywords available]

Indexed keywords

DATA REDUCTION; DATA TRANSFER; MICROPROCESSOR CHIPS; NETWORKS (CIRCUITS); USER INTERFACES;

ACCESS MECHANISMS; TEST PIN INTERFACES; TEST WRAPPERS;

DESIGN FOR TESTABILITY;

EID: 37549065550     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2007.26     Document Type: Conference Paper

References (18)

1. A. Amory et al. Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism. In Proc. ETS, pages 213-218, 2006.
2. L. Benini and G. De Micheli. Networks on Chip: A New SoC Paradigm. IEEE Computer, 35(1):70-80, 2002.
3. T. Bjerregaard and S. Mahadevan. A survey of research and practices on network-on-chip. ACM Computing Surveys, 38(1), 2006.
4. E. Cota, L. Carro, and M. Lubaszewski. Reusing an On-Chip Network for the Test of Core-based Systems. ACM TODAES, 9(4):471-499, 2004.
5. E. Cota et al. Power-aware NoC Reuse on the Testing of Core-based Systems. In Proc. ITC, pages 612-621, 2003.
6. E. Cota et al. The Impact of NoC Reuse on the Testing of Core-based Systems. In Proc. VTS, pages 128-133, 2003.
7. J. Duato, S. Yalamanchili, and L. Ni. Interconnection Networks, An Engineering Approach. Morgan Kaufmann Publishers, 2003.
8. S. Goel and E. Marinissen. SOC Test Architecture Design for Efficient Utilization of Test Bandwidth. ACM TODAES, 8(4):399-429, Oct. 2003.
9. ITRS. International Technology Roadmap for Semiconductors. Semiconductor Industry Association, 2005.
10. S. Koranne. Design of Reconfigurable Access Wrappers for Embedded Core Based SoC Test. IEEE Trans. VLSI Systems, 11(5):955-960, 2003.
11. M. Li et al. An Efficient Wrapper Scan Chain Configuration Method for Network-on-Chip Testing. In Proc. ISVLSI, 2006.
12. C. Liu et al. Test Scheduling for Network-on-Chip with BIST and Precedence Constraints. In Proc. ITC, pages 1369-1378, 2004.
13. C. Liu et al. Power-Aware Test Scheduling in Network-on-Chip Using Variable-Rate On-Chip Clocking. In Proc. VTS, pages 349-354, 2005.
14. C. Liu and V. Iyengar. Test Scheduling with Thermal Optimization for Network-on-Chip Systems Using Variable-Rate On-Chip Clocking. In Proc. DATE, pages 1-6, 2006.
15. E. Marinissen et al. A Structured And Scalable Mechanism for Test Access to Embedded Reusable Cores. In Proc. ITC, pages 284-293, 1998.
16. F. Moraes et al. Hermes: an Infrastructure for Low Area Overhead Packet-switching Networks on Chip. Integration, the VLSI Journal, pages 69-93, 2004.
17. OCP International Partnership. Open Core Protocol Specification. Release 2.0, 2003.
18. H. Zhang. Service disciplines for guaranteed performance service in packet-switching networks. Proc. of the IEEE, 83(10):1374-1396, 1995.