An electrothermally-aware full-chip substrate temperature gradient evaluation methodology for leakage dominant technologies with implications for power estimation and hot-spot management

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2006, Pages 568-574

  Lin, Sheng Chih ^a   Banerjee, Kaustav ^a  

^a University of California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

(OTDR) TECHNOLOGY; ACCURATE ESTIMATION; CHIP-LEVEL; CMOS TECHNOLOGIES; COMPUTER-AIDED DESIGN; CUBIC STRUCTURES; ELECTRO THERMAL COUPLING; EVALUATION METHODOLOGIES; HOT SPOTTING; HOT-SPOTS; INHOMOGENEOUS LAYERS; INTERNATIONAL CONFERENCES; NANO-METER REGIMES; ON CHIPS; POWER DISSIPATIONS; POWER ESTIMATIONS; SILICON (111) SUBSTRATES; SUB THRESHOLD LEAKAGE; SUBSTRATE TEMPERATURE (ST); TRADITIONAL METHODS; VLSI DESIGNS;

DESIGN; GRADIENT METHODS; INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS; LITHOGRAPHY; MOBILE TELECOMMUNICATION SYSTEMS; SUBSTRATES; TECHNOLOGY; TEMPERATURE; TEMPERATURE DISTRIBUTION; THERMAL GRADIENTS; THERMOANALYSIS; THERMOGRAPHY (TEMPERATURE MEASUREMENT);

ESTIMATION;

EID: 36849066113     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2006.320176     Document Type: Conference Paper

References (33)

1. K. Banerjee, PhD Thesis, University of California, Berkeley, 1999.
2. A. H. Ajami et al., "Analysis of Non-Uniform Temperature-Dependent Interconnect Performance in High Performance ICs," in Proc. DAC, pp. 567-572, 2001.
3. International Technology Roadmap for Semiconductors (ITRS)
4. R. S. Prasher et al., "Nano and Micro Technology-Based Next-Generation Package-Level Cooling Solutions" Intel Technology Journal 4th quarter, 2005.
5. K. Banerjee et al., "The Effect of Interconnect Scaling and Low-K Dielectric on the Thermal Characteristics of the IC Metal," in Proc. IEDM, 1996, pp. 65-68.
6. S. Im and K. Banerjee, "Full Chip Thermal Analysis of Planar (2-D) and Vertically Integrated (3-D) High Performance ICs," in Proc. IEDM, 2000, pp. 727-730.
7. K. Banerjee and A. Mehrotra, "Global (Interconnect) Warming," IEEE Circuits Devices Magazine, Vol. 17, pp. 16-32, 2001.
8. A. H. Ajami et al., "Scaling Analysis of On-Chip Power Grid Voltage Variations in Nanometer Scale ULSI," Journal of Analog Integrated Circuits and Signal Processing, Vol. 42, pp. 277-290, 2005.
9. J. Lee, "Thermal Placement Algorithm Based on Heat Conduction Analogy," IEEE Trans. Components and Packaging Technologies, Vol. 26, pp.473-482, 2003.
10. B. Goplen and S. Sapatnekar, "Efficient Thermal Placement of Standard Cells in 3D ICs Using a Force Directed Approach," in Proc. ICCAD, 2003, pp. 86-89.
11. C. N. Chu and D. F. Wong, "A Matrix Synthesis Approach to Thermal Placement," in Proc. ISPD, 1997, pp. 163-168.
12. S-C. Lin et al., "Analysis and Implications of IC Cooling for Deep Nanometer Scale CMOS Technologies," in Proc. IEDM, 2005, pp. 1041-1044.
13. Y. Cheng et al., "A Chip-Level Electrothermal Simulator for Temperature Profile Estimation of CMOS VLSI Chips," in Proc. ISCAS, 1996, pp. 580-583.
14. Y. Cheng et al., "ILLIADS-T: An Electrothermal Timing Simulator for Temperature-Sensitive Reliability Diagnosis of CMOS VLSI Chips," IEEE Trans. on Computer-Aided Design (TCAD), Vol. 17, pp. 668-681, 1998.
15. T. Wang et al., "3-D Thermal-ADI: A Linear-Time Chip Level Transient Thermal Simulator," IEEE Trans. on Computer-Aided Design (TCAD), Vol. 21, pp. 1434-1445, 2002.
16. T. Wang et al., "Thermal-ADI - A Linear-Time Chip-Level Dynamic Thermal-Simulation Algorithm Based on Alternating-Direction-Implicit (ADI) Method," IEEE Trans. on Very Large Scale Integration (VLSI) Systems, Vol. 11, pp. 691-700, 2003.
17. P. Li et al., "Efficient Full-Chip Thermal Modeling and Analysis," in Proc. ICCAD, 2004, pp. 319-326.
18. Y. Zhan and S.S. Sapatnekar, "A High Efficiency Full-Chip Thermal Simulation Algorithm," in Proc. ICCAD, 2004, pp. 634-637.
19. Z. Yu et al., "Fast Placement-Dependent Full Chip Thermal Simulation," in Proc. VLSI-TSA, 2001, pp. 249-252.
20. W. Huang et al., "Compact Thermal Modeling for Temperature-Aware Design," in Proc. DAC, 2004, pp. 878-883.
21. S. Borkar et al., "Parameter Variations and Impact on Circuits and Microarchitecture," in Proc. DAC, 2003, pp. 338-342.
22. S. Narendra et al., "Full-Chip Sub-Threshold Leakage Power Prediction Model for Sub-0.18 urn CMOS," in Proc. ISLPED, 2002, pp. 19-23.
23. P. Gelsinger, 41st Design Automation Conference (DAC) Keynote, 2004.
24. Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices, Cambridge Univ. Press, 1998.
25. V. De and S. Borkar, "Technology and Design Challenges for Low Power and High Performance," in Proc. ISLPED, 1999, pp. 163-168.
26. K. Banerjee et al., "A Self-Consistent Junction Temperature Estimation Methodology for Nanometer Scale ICs with Implications for Performance and Thermal Management," in Proc. IEDM, 2003, pp. 887-890.
27. S. Im et al., "Scaling Analysis of Multilevel Interconnect Temperatures for High Performance ICs," IEEE Transactions on Electron Devices (TED), Vol. 52, pp. 2710-2719, 2005.
28. M. N. Özişik, Boundary value problems of Heat Conduction, Dover Publications, 2002.
29. R. Haberman, "Elementary Applied Partial Differential Equations with Fourier Series and Boundary Value Problems," Prentice Hall, 1983.
30. D. W. Peaceman and H. H. Rachford, "The Numerical Solution of Parabolic and Elliptic Differential Equations," Journal of the Society for Industrial and Applied Mathematics (SIAM), pp. 28-41, 1995.
31. J. Douglas and H. H. Rachford, "On the Numerical Solution of Heat Conduction Problems in Two or Three Space Variables," Trans. American Mathematical Society, pp. 421-439, 1956.
32. A. H. Ajami et al., "Effects of Non-Uniform Substrate Temperature on the Clock Signal Integrity in High Performance Designs," in Proc. CICC, 2001, pp. 233-236.
33. A. H. Ajami et al., "Analysis of Substrate Thermal Gradient Effects on Optimal Buffer Insertion," in Proc. ICCAD, 2001, pp. 44-48.