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Volumn 2005, Issue , 2005, Pages 202-209

VLSI design of a high-throughput multi-rate decoder for structured LDPC codes

Author keywords

[No Author keywords available]

Indexed keywords

CODES (SYMBOLS); COMPUTER ARCHITECTURE; DECODING; LOCAL AREA NETWORKS; LOGIC DESIGN; MICROELECTRONICS; THROUGHPUT;

EID: 33845302959     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2005.77     Document Type: Conference Paper
Times cited : (32)

References (19)
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  • 2
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  • 4
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  • 5
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    • A parallel VLSI architecture for 1-Gb/s, 2048-b, rate-1/2 Turbo Gallager code decoder
    • Aug-Sept.
    • P. Ciao, G. Colavolpe, and L. Fanucci. "A parallel VLSI architecture for 1-Gb/s, 2048-b, rate-1/2 Turbo Gallager code decoder," in Euromicro Symposium on Digital System Design, Aug-Sept. 2004, pp. 174-181.
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    • Ciao, P.1    Colavolpe, G.2    Fanucci, L.3
  • 6
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    • High-throughput LDPC decoders
    • Dec
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    • (2003) IEEE Trans. VLSI Syst. , vol.11 , Issue.6 , pp. 976-996
    • Mansour, M.1    Shanbhag, N.R.2
  • 7
    • 18144396564 scopus 로고    scopus 로고
    • Block-LDPC: A practical LDPC coding system design approach
    • Apr
    • H. Zhong and T. Zhang, "Block-LDPC: A Practical LDPC Coding System Design Approach," IEEE Trans. Circuits Syst. 1, vol. 52, no. 4, pp. 766-775, Apr 2005.
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    • Zhong, H.1    Zhang, T.2
  • 10
    • 33845339759 scopus 로고    scopus 로고
    • 802.16REVe Sponsor Ballot Recirculation comment, July 2004, IEEE C802.16e-04/141r2
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    • LDPC Coding for OFDMA PHY
  • 11
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    • A recursive approach to low complexity codes
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  • 12
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    • Factor graphs and the sum-product algorithm
    • Feb
    • F. Kschischang, B. Frey, and H.-A. Loeliger, "Factor graphs and the sum-product algorithm," IEEE Trans. Inform. Theory, vol. 47, no. 2, pp. 498-519, Feb 2001.
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    • Kschischang, F.1    Frey, B.2    Loeliger, H.-A.3
  • 13
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    • Reduced complexity iterative decoding of low-density parity check codes based on belief propagation
    • May
    • M. Fossorier, M. Mihaljevic, and H. Imai, "Reduced complexity iterative decoding of low-density parity check codes based on belief propagation," IEEE Trans. Commun., vol. 47, no. 5, pp. 673-680, May 1999.
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  • 15
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    • Zarkeshvari, F.1    Banihashetni, A.2
  • 18
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    • (2003)
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  • 19
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    • Decoder architecture for array-code-based LDPC codes
    • Dec
    • S. Olcer, "Decoder architecture for array-code-based LDPC codes," in Global Telecommunications Conference, vol. 4, Dec 2003, pp. 2046-2050.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.