A novel design methodology for high-performance programmable decoder cores for AA-LDPC codes

IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation

Volumn 2003-January, Issue , 2003, Pages 29-34

  Mansour, M M ^a   Shanbhag, N R ^a  

^a University of Illinois at Urbana Champaign   (United States)

Author keywords

Algorithm design and analysis; Decoding; Degradation; Design methodology; Design optimization; Libraries; Memory architecture; Parity check codes; Routing; Scalability

Indexed keywords

ALGORITHMS; COMPLEX NETWORKS; DECODING; DEGRADATION; DESIGN; ERROR CORRECTION; FORWARD ERROR CORRECTION; INTEGRATED CIRCUIT INTERCONNECTS; LIBRARIES; MEMORY ARCHITECTURE; NETWORK ARCHITECTURE; SATELLITE COMMUNICATION SYSTEMS; SCALABILITY; SIGNAL PROCESSING;

ALGORITHM DESIGN AND ANALYSIS; DESIGN METHODOLOGY; DESIGN OPTIMIZATION; PARITY CHECK CODES; ROUTING;

CODES (SYMBOLS);

EID: 84943246554     PISSN: 15206130     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SIPS.2003.1235639     Document Type: Conference Paper

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