A scalable architecture of a structured LDPC decoder

IEEE International Symposium on Information Theory - Proceedings

Volumn , Issue , 2004, Pages 292-

  Lee, Jason Kwok San ^a   Lee, Benjamin ^a   Thorpe, Jeremy ^a   Andrews, Kenneth ^a   Dolinar, Sam ^a   Hamkins, Jon ^a  

^a CALIFORNIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DECODER ARCHITECTURE; DECODING GRAPH; DECODING SPEED; LDPC CODES;

ALGORITHMS; CODES (SYMBOLS); COMPUTER HARDWARE; COMPUTER SOFTWARE; DECODING; FIELD PROGRAMMABLE GATE ARRAYS; OPTIMIZATION;

COMPUTER ARCHITECTURE;

EID: 5044251617     PISSN: 21578097     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (1)

1. J. Thorpe, "Low-Density Parity-Check (LDPC) Codes Constructed from Protographs," IPN Progress Reports 42-154, April-June 2003.