Field programmable gate array implementation of a generalized decoder for structured low-density parity check codes

Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04

Volumn , Issue , 2004, Pages 17-24

  Sun, Lingyan ^a   Kumar, B V K Vijaya ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BIT ERROR RATE; CODES (SYMBOLS); COMPUTER SIMULATION; CONFORMAL MAPPING; CONSTRAINT THEORY; DECODING; ERROR CORRECTION; MATRIX ALGEBRA; MONTE CARLO METHODS; PROBABILITY; RANDOM PROCESSES;

ERROR CORRECTION CODES (ECC); LOW-DENSITY PARITY CHECK (LDPC) CODES; MEMORY MANAGEMENT; REED-SOLOMON CODES;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 20844448544     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)

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