Impact of Data Cache Memory on the Single Event Upset-Induced Error Rate of Microprocessors

IEEE Transactions on Nuclear Science

Volumn 50, Issue 6 I, 2003, Pages 2101-2106

  Faure, F ^a   Velazco, R ^a   Violante, M ^b   Rebaudengo, M ^b   Reorda, M Sonza ^b  

^a TIMA LABORATORY   (France)

^b POLITECNICO DI TORINO   (Italy)

Author keywords

Cache memories; Fault injection; Microprocessors; Radiation effects; Single event upsets (SEUs)

Indexed keywords

BENCHMARKING; CODES (SYMBOLS); COMPUTER HARDWARE; COMPUTER SIMULATION; FLOW CONTROL; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; PROGRAM PROCESSORS; RADIATION EFFECTS; REGRESSION ANALYSIS; SUPERVISORY AND EXECUTIVE PROGRAMS;

ERROR RATES; FAULT INJECTION; SINGLE EVENT UPSETS (SEU);

BUFFER STORAGE;

EID: 1242265245     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2003.821824     Document Type: Conference Paper

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