N-Channel (110)-sidewall strained FinFETs with silicon-carbon source and drain stressors and tensile capping layer

IEEE Electron Device Letters

Volumn 28, Issue 11, 2007, Pages 1014-1017

  Liow, Tsung Yang ^a,b   Tan, Kian Ming ^a   Lee, Rinus T P ^a   Tung, Chih Hang ^b   Samudra, Ganesh S ^a   Balasubramanian, N ^b   Yeo, Yee Chia ^a  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^b INSTITUTE OF MICROELECTRONICS   (Singapore)

Author keywords

Etch stop layer (ESL); Fin shaped field effect transistor (FinFET); Multiple gate transistor; Silicon carbon (SiC); Strain; Stress

Indexed keywords

COMPRESSIVE STRESS; ELECTRON MOBILITY; LATTICE MISMATCH; SILICON NITRIDE; TENSILE STRESS;

ETCH-STOP LAYER; FIN-SHAPED FIELD-EFFECT TRANSISTOR; MULTIPLE-GATE TRANSISTOR;

FIELD EFFECT TRANSISTORS;

EID: 36148937605     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2007.908495     Document Type: Article

References (20)

1. D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Andersen, T.-J. King, I. Bokor, and C. Hu, "FinFET - A self-aligned double-gate MOSFET scalable to 20 nm," IEEE Trans. Electron Devices vol. 47, no. 12, pp. 2320-2325, Dec. 2000.
2. B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C.-Y. Yang, C. Tabery, C. Ho, Q. Xiang, T.-J. King, J. Bokor, C. Hu, M.-R. Lin, and D. Kyser, "FinFET scaling to 10 nm gate length," in IEDM Tech. Dig., 2002, pp. 251-254.
3. F.-L. Yang, D.-H. Lee, H.-Y. Chen, C.-Y. Chang, S.-D. Liu, C.-C. Huang, T.-X. Chung, H.-W. Chen, C.-C. Huang, Y.-H. Liu, C.-C. Wu, C.-C. Chen, S.-C. Chen, Y.-T. Chen, Y.-H. Chen, C.-J. Chen, B.-W. Chan, P.-F. Hsu, J.-H. Shieh, H.-J. Tao, Y.-C. Yeo, Y. Li, J.-W. Lee, P. Chen, M.-S. Liang, and C. Hu, "5 nm-gate nanowire FinFET," in VLSI Symp. Tech. Dig., 2004, pp. 196-197.
4. L. Chang, Y. K. Choi, D. Ha, P. Ranade, S. Xiong, J. Bokor, C. Hu, and T.-J. King, "Extremely scaled silicon nano-CMOS devices," Proc. IEEE, vol. 91, no. 11, pp. 1860-1873, Nov. 2003.
5. Z. Guo, S. Balasubramanian, R. Ziatanovici, T.-J. King, and B. Nikolic, "FinFET-based SRAM design," in Proc. ISLPED, 2005, pp. 2-7.
6. K. Uchida, A. Kinoshita, and M. Saitoh, "Carrier transport in (110) nMOSFETs: Subband structures, non-parabolicity, mobility characteristics, and uniaxial stress engineering," in IEDM Tech. Dig., 2006, pp. 1-3.
7. W. Xiong, C. R. Cleavelin, P. Kohli, C. Huffman, T. Schulz, K. Schruefer, G. Gebara, K. Mathews, P. Patruno, Y.-M. Le Vaillant, I. Cayrefourcq, M. Kennard, C. Mazure, K. Shin, and T.-J. K. Liu, "Impact of strained-silicon-on-insulator (sSOI) substrate on FinFET mobility," in IEDM Tech. Dig., Dec. 2006, pp. 1019-1021.
8. T. Irisawa, T. Numata, T. Tezuka, N. Sugiyama, and S. Takagi, "Electron transport properties of ultrathin-body and tri-gate SOI nMOSFETs with biaxial and uniaxial strain," in IEDM Tech. Dig., 2006, pp. 457-460.
9. N. Collaert, A. De Keersgieter, K. G. Anil, R. Rooyackers, G. Eneman, M. Goodwin, B. Eyckens, E. Sleeckx, J.-F. de Marneffe, K. De Meyer, P. Absil, M. Jurczak, and S. Biesemans, "Performance improvement of tall triple gate devices with strained SiN layers," IEEE Electron Device Lett., vol. 26, no. 11, pp. 820-822, Nov. 2005.
10. K. Shin, C. O. Chui, and T.-J. King, "Dual stress capping layer enhancement study for hybrid orientation FinFET CMOS technology," in IEDM Tech. Dig., 2005, pp. 1009-1012.
11. J. Kavalieros, B. Doyle, S. Datta, G. Dewey, M. Doczy, B. Jin, D. Lionberger, M. Metz, W. Rachmady, M. Radosavljevic, U. Shah, N. Zelick, and R. Chau, "Tri-gate transistor architecture with high-k gate dielectrics, metal gates and strain engineering," in VLSI Symp. Tech. Dig., 2006, pp. 62-63.
12. N. Collaert, R. Rooyackers, F. Clemente, P. Zimmerman, I. Cayrefourcq, B. Ghyselen, K. T. San, B. Eyckens, M. Jurczak, and S. Biesemans, "Performance enhancement of MuGFET devices using super critical strained-SOI (SC-SSOI) and CESL," in VLSI Symp. Tech. Dig., 2006, pp. 64-65.
13. J. Kedzierski, M. Ieong, E. Nowak, T. S. Kanarsky, Y. Zhang, R. Roy, D. Boyd, D. Fried, and H.-S. P. Wong, "Extension and source/drain design for high-performance FinFET devices," IEEE Trans. Electron Devices vol. 50, no. 4, pp. 952-958, Apr. 2003.
14. Y.-C. Yeo, "Enhancing CMOS transistor performance using lattice-mismatched materials in source/drain regions," Semicond. Sci. Technol., vol. 22, no. 1, pp. S177-S182, Jan. 2007.
15. T.-Y. Liow, K.-M. Tan, R. T. P. Lee, A. Du, C.-H. Tung, G. S. Samudra, W.-J. Yoo, N. Balasubramanian, and Y.-C. Yeo, "Strained n-channel FinFETs with 25 nm gate length and silicon-carbon source/drain regions for performance enhancement," in VLSI Symp. Tech. Dig., 2006, pp. 68-69.
16. Y. Ishikawa, M. Kumezawa, R. Nuryadi, and M. Tabe, "Effect of patterning on thermal agglomeration of ultrathin silicon-on-insulator layer," Appl. Surf. Sci., vol. 190, no. 1, pp. 11-15, May 2002.
17. Y. Ishikawa, Y. Imai, H. Ikeda, and M. Tabe, "Pattern-induced alignment of silicon islands on buried oxide layer of silicon-on-insulator structure," Appl. Phys. Lett., vol. 83, no. 15, pp. 3162-3164, Oct. 2003.
18. 2 in ultrahigh vacuum," J. Vac. Sci. Technol. B, Microelectron. Process. Phenom., vol. 20, no. 1, pp. 167-172, Jan./Feb. 2002.
19. C. S. Smith, "Piezoresistance effect in germanium and silicon," Phys. Rev., vol. 94, no. 1, pp. 42-49, Apr. 1954.
20. Y. Kanda, "A graphical representation of the piezoresistance coefficients in silicon," IEEE Trans. Electron Devices, vol. ED-29, no. 1, pp. 64-70, Jan. 1982.