Enhancing CMOS transistor performance using lattice-mismatched materials in source/drain regions

Semiconductor Science and Technology

Volumn 22, Issue 1, 2007, Pages

  Yeo, Yee Chia ^a  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRON MOBILITY; LATTICE CONSTANTS; LATTICE MISMATCH; STRAIN RATE;

CMOS TRANSISTOR; COMPRESSIVE STRAIN; SOURCE/DRAIN REGIONS; STRAIN ENGINEERING;

TRANSISTORS;

EID: 34247235178     PISSN: 02681242     EISSN: 13616641     Source Type: Journal    
DOI: 10.1088/0268-1242/22/1/S42     Document Type: Article

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