-
1
-
-
14844320546
-
On the great potential of non-doped MOSFETs for analog applications in partially depleted SOI CMOS process
-
May
-
V. Kilchytska, D. Levacq, L. Vancaillie, and D. Flandre, "On the great potential of non-doped MOSFETs for analog applications in partially depleted SOI CMOS process," Solid State Electron., vol. 49, no. 5, pp. 708-715, May 2005.
-
(2005)
Solid State Electron
, vol.49
, Issue.5
, pp. 708-715
-
-
Kilchytska, V.1
Levacq, D.2
Vancaillie, L.3
Flandre, D.4
-
2
-
-
24144468950
-
Impact of halo implantation on 0.13 μm floating body partially depleted SOI n-MOSFETs in low temperature operation
-
Aug
-
M. A. Pavanello, J. A. Martino, E. Simoen, and C. Claeys, "Impact of halo implantation on 0.13 μm floating body partially depleted SOI n-MOSFETs in low temperature operation," Solid State Electron., vol. 49, no. 8, pp. 1274-1281, Aug. 2005.
-
(2005)
Solid State Electron
, vol.49
, Issue.8
, pp. 1274-1281
-
-
Pavanello, M.A.1
Martino, J.A.2
Simoen, E.3
Claeys, C.4
-
3
-
-
0035691874
-
Analog device design for low power mixed mode applications in deep submicron CMOS technology
-
Dec
-
H. V. Deshpande, B. Cheng, and J. C. S. Woo, "Analog device design for low power mixed mode applications in deep submicron CMOS technology," IEEE Electron Device Lett., vol. 22, no. 12, pp. 588-590, Dec. 2001.
-
(2001)
IEEE Electron Device Lett
, vol.22
, Issue.12
, pp. 588-590
-
-
Deshpande, H.V.1
Cheng, B.2
Woo, J.C.S.3
-
4
-
-
0032630536
-
A study of self-aligned doped channel MOSFET structure for low power and low 1/fi] noise operation
-
Jul
-
T. Yoshitomi, H. Kimijima, S. Ishizuka, Y. Miyahara, T. Ohguro, E. Morifuji, T. Morimoto, H. S. Momose, Y. Katsumata, and H. Iwai, "A study of self-aligned doped channel MOSFET structure for low power and low 1/fi] noise operation," Solid State Electron., vol. 43, no. 7, pp. 1219-1224, Jul. 1999.
-
(1999)
Solid State Electron
, vol.43
, Issue.7
, pp. 1219-1224
-
-
Yoshitomi, T.1
Kimijima, H.2
Ishizuka, S.3
Miyahara, Y.4
Ohguro, T.5
Morifuji, E.6
Morimoto, T.7
Momose, H.S.8
Katsumata, Y.9
Iwai, H.10
-
5
-
-
0033736623
-
Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects
-
Jun
-
M. A. Pavanello, J. A. Martino, and D. Flandre, "Graded-channel fully depleted silicon-on-insulator nMOSFET for reducing the parasitic bipolar effects," Solid State Electron., vol. 44, no. 6, pp. 917-922, Jun. 2000.
-
(2000)
Solid State Electron
, vol.44
, Issue.6
, pp. 917-922
-
-
Pavanello, M.A.1
Martino, J.A.2
Flandre, D.3
-
6
-
-
0033751937
-
Analog performance and application of graded-channel fully depleted SOI MOSFETs
-
Jul
-
M. A. Pavanello, J. A. Martino, and D. Flandre, "Analog performance and application of graded-channel fully depleted SOI MOSFETs," Solid State Electron., vol. 44, no. 7, pp. 1219-1222, Jul. 2000.
-
(2000)
Solid State Electron
, vol.44
, Issue.7
, pp. 1219-1222
-
-
Pavanello, M.A.1
Martino, J.A.2
Flandre, D.3
-
7
-
-
1442287310
-
Laterally asymmetric channel engineering in fully depleted double gate SOI MOSFETs for high performance analog applications
-
Jun
-
A. Kranti, T. M. Chung, D. Flandre, and J. P. Raskin, "Laterally asymmetric channel engineering in fully depleted double gate SOI MOSFETs for high performance analog applications," Solid State Electron., vol. 48, no. 6, pp. 947-959, Jun. 2004.
-
(2004)
Solid State Electron
, vol.48
, Issue.6
, pp. 947-959
-
-
Kranti, A.1
Chung, T.M.2
Flandre, D.3
Raskin, J.P.4
-
8
-
-
18844377426
-
Advantages of the graded-channel SOI FD MOSFET for application as a quasi-linear resistor
-
May
-
A. Cerdeira, M. A. Alemán, M. A. Pavanello, J. A. Martino, L. Vancaillie, and D. Flandre, "Advantages of the graded-channel SOI FD MOSFET for application as a quasi-linear resistor," IEEE Trans. Electron Devices, vol. 52, no. 5, pp. 967-972, May 2005.
-
(2005)
IEEE Trans. Electron Devices
, vol.52
, Issue.5
, pp. 967-972
-
-
Cerdeira, A.1
Alemán, M.A.2
Pavanello, M.A.3
Martino, J.A.4
Vancaillie, L.5
Flandre, D.6
-
9
-
-
33847274701
-
The low-frequency noise behaviour of graded-channel SOI nMOSFETs
-
Feb
-
E. Simoen, C. Claeys, T. M. Chung, D. Flandre, M. A. Pavanello, J. A. Martino, and J.-P. Raskin, "The low-frequency noise behaviour of graded-channel SOI nMOSFETs," Solid State Electron., vol. 51, no. 2, pp. 260-267, Feb. 2007.
-
(2007)
Solid State Electron
, vol.51
, Issue.2
, pp. 260-267
-
-
Simoen, E.1
Claeys, C.2
Chung, T.M.3
Flandre, D.4
Pavanello, M.A.5
Martino, J.A.6
Raskin, J.-P.7
-
10
-
-
34948869623
-
The length-dependence of the 1/f noise of graded-channel SOI nMOSFETs
-
J. A. Martino, M. A. Pavanello, and C. Claeys, Eds
-
E. Simoen, C. Claeys, T. M. Chung, D. Flandre, and J.-P. Raskin, "The length-dependence of the 1/f noise of graded-channel SOI nMOSFETs," J. A. Martino, M. A. Pavanello, and C. Claeys, Eds., Electrochem. Soc. Trans., vol. 9, no. 1, pp. 376-382, 2007.
-
(2007)
Electrochem. Soc. Trans
, vol.9
, Issue.1
, pp. 376-382
-
-
Simoen, E.1
Claeys, C.2
Chung, T.M.3
Flandre, D.4
Raskin, J.-P.5
-
11
-
-
0028550128
-
1/f noise sources
-
Nov
-
F. N. Hooge, "1/f noise sources," IEEE Trans. Electron Devices, vol. 41, no. 11, pp. 1926-1935, Nov. 1994.
-
(1994)
IEEE Trans. Electron Devices
, vol.41
, Issue.11
, pp. 1926-1935
-
-
Hooge, F.N.1
-
12
-
-
0026144142
-
Improved analysis of low frequency noise in field-effect MOS transistors
-
G. Ghibaudo, O. Roux, C. Nguyen-Duc, F. Balestra, and J. Brini, "Improved analysis of low frequency noise in field-effect MOS transistors," Phys. Stat. Sol. A, vol. 124, no. 2, pp. 571-581, 1991.
-
(1991)
Phys. Stat. Sol. A
, vol.124
, Issue.2
, pp. 571-581
-
-
Ghibaudo, G.1
Roux, O.2
Nguyen-Duc, C.3
Balestra, F.4
Brini, J.5
-
13
-
-
0025398785
-
A unified model for the flicker noise in metal-oxide-semiconductor field-effect transistors
-
Mar
-
K. K. Hung, P. K. Ko, C. Hu, and Y. C. Cheng, "A unified model for the flicker noise in metal-oxide-semiconductor field-effect transistors," IEEE Trans. Electron Devices, vol. 37, no. 3, pp. 654-665, Mar. 1990.
-
(1990)
IEEE Trans. Electron Devices
, vol.37
, Issue.3
, pp. 654-665
-
-
Hung, K.K.1
Ko, P.K.2
Hu, C.3
Cheng, Y.C.4
-
14
-
-
0028549082
-
The impact of device scaling on the current fluctuations in MOSFET's
-
Nov
-
M.-H. Tsai and T.-P. Ma, "The impact of device scaling on the current fluctuations in MOSFET's," IEEE Trans. Electron Devices, vol. 41, no. 11, pp. 2061-2068, Nov. 1994.
-
(1994)
IEEE Trans. Electron Devices
, vol.41
, Issue.11
, pp. 2061-2068
-
-
Tsai, M.-H.1
Ma, T.-P.2
-
15
-
-
33846592716
-
Low-frequency noise in silicon-on-insulator devices and technologies
-
Jan
-
E. Simoen, A. Mercha, C. Claeys, and N. Lukyanchikova, "Low-frequency noise in silicon-on-insulator devices and technologies," Solid State Electron., vol. 51, no. 1, pp. 16-37, Jan. 2007.
-
(2007)
Solid State Electron
, vol.51
, Issue.1
, pp. 16-37
-
-
Simoen, E.1
Mercha, A.2
Claeys, C.3
Lukyanchikova, N.4
-
16
-
-
0036477162
-
Low-frequency noise in deep-submicron metal-oxide-semiconductor field-effect transistors
-
Feb
-
Z. Çelik-Butler, "Low-frequency noise in deep-submicron metal-oxide-semiconductor field-effect transistors," Proc. Inst. Electr. Eng. G-Circuits Devices Syst., vol. 149, no. 1, pp. 23-31, Feb. 2002.
-
(2002)
Proc. Inst. Electr. Eng. G-Circuits Devices Syst
, vol.149
, Issue.1
, pp. 23-31
-
-
Çelik-Butler, Z.1
-
17
-
-
0347968287
-
Generation-recombination noise in the near fully depleted SIMOX SOI nMOSFET - Physical characteristics and modeling
-
Dec
-
D. S. Ang, Z. Lun, and C. H. Ling, "Generation-recombination noise in the near fully depleted SIMOX SOI nMOSFET - Physical characteristics and modeling," IEEE Trans. Electron Devices, vol. 50, no. 12, pp. 2490-2498, Dec. 2003.
-
(2003)
IEEE Trans. Electron Devices
, vol.50
, Issue.12
, pp. 2490-2498
-
-
Ang, D.S.1
Lun, Z.2
Ling, C.H.3
-
18
-
-
0030107494
-
Back and front interface related generation-recombination noise in buried-channel SOI pMOSFETs
-
Mar
-
N. Lukyanchikova, M. Petrichuk, N. Garbar, E. Simoen, and C. Claeys, "Back and front interface related generation-recombination noise in buried-channel SOI pMOSFETs," IEEE Trans. Electron Devices, vol. 43, no. 3, pp. 417-423, Mar. 1996.
-
(1996)
IEEE Trans. Electron Devices
, vol.43
, Issue.3
, pp. 417-423
-
-
Lukyanchikova, N.1
Petrichuk, M.2
Garbar, N.3
Simoen, E.4
Claeys, C.5
-
19
-
-
0033188873
-
2 interface
-
Sep
-
2 interface," Semicond. Sci. Technol., vol. 14, no. 9, pp. 775-783, Sep. 1999.
-
(1999)
Semicond. Sci. Technol
, vol.14
, Issue.9
, pp. 775-783
-
-
Lukyanchikova, N.B.1
Petrichuk, M.V.2
Garbar, N.P.3
Simoen, E.4
Claeys, C.5
|