Study of self-aligned doped channel MOSFET structure for low power and low 1/f noise operation

Solid-State Electronics

Volumn 43, Issue 7, 1999, Pages 1219-1224

  Yoshitomi, Takashi ^a   Kimijima, Hideki ^a   Ishizuka, Shinnichiro ^a   Miyahara, Yasunori ^a   Ohguro, Tatsuya ^a   Morifuji, Eiji ^a   Morimoto, Toyota ^a   Sasaki Momose, Hisayo ^a   Katsumata, Yasuhiro ^a   Iwai, Hiroshi ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; DIFFUSION; GATES (TRANSISTOR); MOSFET DEVICES; SEMICONDUCTOR DOPING;

CHANNEL DOPING; GATE LENGTH; IMPLANTATION DAMAGE; SELF ALIGNED DOPED CHANNEL; SOLID PHASE DIFFUSION;

SEMICONDUCTOR DEVICE STRUCTURES;

EID: 0032630536     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0038-1101(99)00066-0     Document Type: Article

References (4)

1. Chatterjee A, Chapman RA, Dixit G, Kuehnr J, Hattangady S, Yang H et al. Sub-100 nm gate length metal gate NMOS transistors fabricated by a replacement gate process. IEDM Tech Dig 1997:821-4.
2. Wakabayashi H, Yamamoto T, Tatsumi T, Tokunaga K, Tamura T, Mogami T, Kunio T. A high-performance 0.1 μm CMOS with elevated salicide using novel Si-SEG process. IEDM Tech Dig 1997;99-102.
3. Togo M, Tanabe A, Furukawa A, Tokunaga K, Hashimoto T. A Gate-side Air-gap Structure (GAS) to reduce the parasitic capacitance in MOSFETs, Symp on VLSI Tech. Digest, 1996. p. 38-9.
4. Takagi S, Iwase M, Toriumi A. On the universality of inversion-layer mobility in N- and P-channel MOSFETs. IEDM Tech Dig 1988;398-401.