3-D capacitive interconnections for wafer-level and die-level assembly

IEEE Journal of Solid-State Circuits

Volumn 42, Issue 10, 2007, Pages 2270-2281

  Fazzi, Alberto ^b,c   Magagni, Luca ^b   Mirandola, Mauro ^b   Charlet, Barbara ^e   Di Cioccio, Léa ^e   Jung, Erik ^a,f   Canegallo, Roberto ^d   Guerrieri, Roberto ^b  

^a IEEE

^b UNIVERSITY OF BOLOGNA   (Italy)

^c PHILIPS RESEARCH LABORATORIES   (Netherlands)

^d STMICROELECTRONICS   (Italy)

^e CEA LETI   (France)

^f FRAUNHOFER IZM   (Germany)

Author keywords

3 D integration; Assembly; Capacitive interconnections; Contactless; Die level; SiP; Wafer level

Indexed keywords

BANDWIDTH; CAPACITANCE; ENERGY UTILIZATION; OPTIMIZATION; WAFER BONDING;

AC INTERCONNECTIONS; DIE-LEVEL ASSEMBLY; INTERCONNECTION SENSITIVITY; SYNCHRONOUS COMMUNICATION CIRCUITS; WAFER-TO-WAFER ASSEMBLY TECHNIQUES;

INTERCONNECTION NETWORKS;

EID: 34748883633     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2007.905230     Document Type: Conference Paper

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